ADZS-ICE-100B Analog Devices Inc, ADZS-ICE-100B Datasheet - Page 18

• Manufacturer Part Number: ADZS-ICE-100B
• Description: EMULATOR BLACKFIN
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Emulatorr

Specifications of ADZS-ICE-100B

• Contents: Board, Cable
• Silicon Family Name: Blackfin
• Core Architecture: Blackfin
• Ic Product Type: Emulator
• Features: Single-Step And Full-Speed Execution, 5MHz JTAG TCLK Frequency, Multiprocessor Support
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Blackfin™ Processors
• Lead Free Status / Rohs Status: Compliant

VisualDSP++ Configurator
VisualDSP++ Configurator
JTAG Frequency
1-8
VisualDSP++ requires a description of the platform (JTAG chain). The
platform definition is necessary for VisualDSP++ to communicate with
the hardware through the emulator.
The VisualDSP++ Configurator and ICE Test utilities allow configuration
and testing of the emulator hardware. ICE Test provides emulator detec-
tion and JTAG interface testing. Use the ICE Test to test the target. If
errors are encountered, they are reported immediately and the test ends.
Refer to VisualDSP++ online Help for information about the
VisualDSP++ Configurator and the ICE Test utility
The ICE-100B emulator supports JTAG clock operation at 5 MHz. There
is a relationship between the JTAG frequency and the core clock fre-
quency of the processor. The core clock should be at least twice the JTAG
frequency in order for the JTAG interface to operate properly. On newer
Analog Devices processors, the core clock is a variable that is sometimes
set by switches or by software.

If the core/JTAG clock relation is not followed, scan failures may
prevent the emulator from connecting to the processor.
ICE-100B Emulator User Guide