AD9777-EB Analog Devices Inc, AD9777-EB Datasheet - Page 22

• Manufacturer Part Number: AD9777-EB
• Description: BOARD EVAL FOR AD9777
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9777-EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 160M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9777

AD9777
FUNCTIONAL DESCRIPTION
The AD9777 dual interpolating DAC consists of two data
channels that can be operated independently or coupled to form
a complex modulator in an image reject transmit architecture.
Each channel includes three FIR filters, making the AD9777
capable of 2×, 4×, or 8× interpolation. High speed input and
output data rates can be achieved within the following
limitations.
Interpolation Rate
(MSPS)
1×
2×
4×
8×
Both data channels contain a digital modulator capable of
mixing the data stream with an LO of f
where f
feature is also included and can be used to improve pass-band
flatness for signals being attenuated by the SIN(x)/x
characteristic of the DAC output. The speed of the AD9777,
combined with its digital modulation capability, enables direct
IF conversion architectures at 70 MHz and higher.
The digital modulators on the AD9777 can be coupled to form
a complex modulator. By using this feature with an external
analog quadrature modulator, such as the Analog Devices
AD8345, an image rejection architecture can be enabled. To
optimize the image rejection capability, as well as LO feed-
through in this architecture, the AD9777 offers programmable
(via the SPI port) gain and offset adjust for each DAC.
Also included on the AD9777 are a phase-locked loop (PLL)
clock multiplier and a 1.20 V band gap voltage reference. With
the PLL enabled, a clock applied to the CLK+/CLK− inputs is
frequency multiplied internally and generates all necessary
internal synchronization clocks. Each 16-bit DAC provides two
complementary current outputs whose full-scale currents can
be determined either from a single external resistor or inde-
pendently from two separate resistors (see the 1R/2R Mode
section). The AD9777 features a low jitter, differential clock
input that provides excellent noise rejection while accepting a
sine or square wave input. Separate voltage supply inputs are
provided for each functional block to ensure optimum noise
and distortion performance.
Sleep and power-down modes can be used to turn off the DAC
output current (sleep) or the entire digital and analog sections
(power-down) of the chip. A SPI-compliant serial port is used
to program the many features of the AD9777. Note that in
power-down mode, the SPI port is the only section of the chip
still active.
DAC
is the output data rate of the DAC. A zero stuffing
Input Data Rate
(MSPS)
160
160
100
50
DAC
/2, f
DAC Sample Rate
(MSPS)
160
320
400
400
DAC
/4, or f
DAC
/8,
Rev. C | Page 22 of 60
SERIAL INTERFACE FOR REGISTER CONTROL
The AD9777 serial port is a flexible, synchronous serial
communications port that allows easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer
formats, including both the Motorola SPI® and Intel® SSR
protocols. The interface allows read/write access to all registers
that configure the AD9777. Single- or multiple-byte transfers
are supported as well as MSB first or LSB first transfer formats.
The AD9777’s serial interface port can be configured as a single
pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD9777. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9777 coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9777 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the upcom-
ing data transfer is read or write, the number of bytes in the
data transfer, and the starting register address for the first byte
of the data transfer. The first eight SCLK rising edges of each
communication cycle are used to write the instruction byte into
the AD9777.
A Logic 1 on the SPI_CSB pin, followed by a logic low, resets
the SPI port timing to the initial state of the instruction cycle.
This is true regardless of the present state of the internal
registers or the other signal levels present at the inputs to the
SPI port. If the SPI port is in the middle of an instruction cycle
or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9777 and the system controller. Phase 2 of the
communication cycle is a transfer of one to four data bytes, as
determined by the instruction byte. Normally, using one multi-
byte transfer is the preferred method. However, single byte data
transfers are useful to reduce CPU overhead when register
access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
SPI_CLK (PIN 55)
SDIO (PIN 54)
SDO (PIN 53)
CSB (PIN 56)
Figure 32. SPI Port Interface
AD9777 SPI PORT
INTERFACE