EVAL-AD7655CB Analog Devices Inc, EVAL-AD7655CB Datasheet - Page 24

• Manufacturer Part Number: EVAL-AD7655CB
• Description: BOARD EVAL FOR AD7655
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7655CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 4 Single Ended
• Input Range: 0 ~ 2 V
• Power (typ) @ Conditions: 120mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7655
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7655
MICROPROCESSOR INTERFACING
The AD7655 is ideally suited for traditional dc measurement
applications supporting a microprocessor and for ac signal
processing applications interfacing to a digital signal processor.
The AD7655 is designed to interface with either a parallel
8-bit-wide or 16-bit-wide interface, a general-purpose serial port,
or I/O ports on a microcontroller. A variety of external buffers
can be used with the AD7655 to prevent digital noise from
coupling into the ADC. The following section describes the use of
the AD7655 with an SPI-equipped DSP, the ADSP-219x.
SPI INTERFACE (ADSP-219
Figure 33 shows an interface diagram between the AD7655 and
the SPI1-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7655 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature to be used. The convert command can be initiated
in response to an internal timer interrupt. The 32-bit output
data is read with two serial peripheral interface (SPI) 16-bit
wide accesses. The reading process can be initiated in response
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to the end of conversion signal (BUSY going low) using an
interrupt line of the DSP. The SPI on the ADSP-219x is
configured for master mode—(MSTR) = 1, Clock Polarity bit
(CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt
Enable (TIMOD) = 00—by writing to the SPI control register
(SPICLTx). To meet all timing requirements, the SPI clock
should be limited to 17 Mbps, which allows it to read an ADC
result in less than 1 μs. When a higher sampling rate is desired,
use of one of the parallel interface modes is recommended.
DVDD
SER/PAR
EXT/INT
RD
INVSCLK
Figure 33. Interfacing the AD7655 to SPI Interface
AD7655*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDOUT
CNVST
BUSY
SCLK
CS
SPIxSEL (PFx)
MISOx
SCKx
PFx
PFx or TFSx
ADSP-219x*