EVAL-AD7686CB Analog Devices Inc, EVAL-AD7686CB Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD7686CB
• Description: BOARD EVALUATION FOR AD7686
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7686CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 15mW @ 500kSPS, 5 V
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7686
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7686
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7686 is connected
to an SPI-compatible digital host, which has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in applications
where low jitter on CNV is desired. The connection diagram is
shown in Figure 39, and the corresponding timing is provided
in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When
conversion is complete, SDO goes from high impedance to low.
ACQUISITION
CNV
SCK
SDO
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 40. CS Mode 4-Wire with Busy Indicator Serial Interface Timing
t
EN
1
Rev. B | Page 20 of 28
t
t
HSDO
DSDO
D15
2
t
CYC
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever occurs first,
the SDO returns to high impedance.
D14
3
ACQUISITION
Figure 39. CS Mode 4-Wire with Busy Indicator Connection Diagram
t
ACQ
t
SCKL
t
SCKH
15
SDI
AD7686
t
SCK
CNV
SCK
16
D1
SDO
17
D0
VIO
47kΩ
t
DIS
CLK
CS1
CONVERT
DATA IN
IRQ
DIGITAL HOST