EVAL-AD7686CB Analog Devices Inc, EVAL-AD7686CB Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7686CB
• Description: BOARD EVALUATION FOR AD7686
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7686CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 15mW @ 500kSPS, 5 V
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7686
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
SDO
ACQUISITION
SDI
A
t
= SDI
HSCKCNV
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
AD7686
CNV
SCK
A
D
D
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
1
A
B
15
15
t
SSDISCK
SDO
D
D
2
A
B
14
14
D
D
3
A
B
13
13
Rev. B | Page 21 of 28
t
SCKL
SDI
t
HSDISCK
14
AD7686
CNV
SCK
B
t
D
D
15
CYC
A
B
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
1
1
ACQUISITION
t
SDO
SCK
t
t
SCKH
D
D
ACQ
16
A
B
0
0
D
17
A
15
CONVERT
DATA IN
CLK
D
18
A
DIGITAL HOST
14
30
D
31
A
1
D
32
A
0
AD7686