PIC12HV615-I/SN Microchip Technology, PIC12HV615-I/SN Datasheet
PIC12HV615-I/SN
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PIC12HV615-I/SN Summary of contents
Page 1
... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2006 Microchip Technology Inc. PIC12F609/HV609 PIC12F615/HV615 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers Preliminary DS41302A ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical Note: Voltage across the shunt regulator should not exceed 5V. © 2006 Microchip Technology Inc. Peripheral Features: • Shunt Voltage Regulator (PIC12HV609/615 only volt regulation - shunt range • 5 I/O pins and 1 input only • ...
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... PIC12F609/615/12HV609/615 Program Memory Device Flash (words) PIC12F609 1024 PIC12HV609 1024 PIC12F615 1024 PIC12HV615 1024 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, TSSOP, DFN) GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/V TABLE 1: PIC12F609/HV609 PIN SUMMARY ( I/O Pin Comparators GP0 7 CIN+ GP1 6 CIN0- GP2 5 COUT (1) GP3 4 — GP4 ...
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... AN3 CIN1- GP5 2 — — — 1 — — — 8 — — * Alternate pin function. Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 GP0/AN0/CIN+/P1B/ICSPDAT 2 7 PIC12F615/ HV615 GP1/AN1/CIN0-/ GP2/AN2/T0CKI/INT/COUT/CCP1/P1A PDIP, SOIC, TSSOP, DFN ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41302A-page 4 Preliminary © 2006 Microchip Technology Inc. ...
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... Generation OSC2/CLKOUT Internal Oscillator Block T1G T1CKI Timer0 T0CKI © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F609/HV609 (Figure 1-1, Table 1-1) • PIC12F615/HV615 (Figure 1-2, Table 1-2) INT 13 Data Bus Program Counter ...
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... STATUS Reg 8 3 Power-up MUX Timer Oscillator Start-up Timer ALU Power-on Reset 8 Watchdog W Reg Timer Brown-out Reset Shunt Regulator (PIC12HV615 only MCLR DD SS Timer1 Timer2 Comparator Voltage Reference Analog Comparator and Reference Absolute Voltage Reference Preliminary 8 GPIO GP0 GP1 GP2 GP3 ...
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... GP5 T1CKI OSC1 CLKIN Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Input Output Type Type TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change AN — Comparator non-inverting input ST CMOS Serial Programming Data I/O ...
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... PWM output, alternate pin OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection V Power — Positive supply DD V Power — Ground reference SS CMOS=CMOS compatible input or output = TTL compatible input Preliminary Description HV = High Voltage XTAL= Crystal © 2006 Microchip Technology Inc. ...
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... Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory Wraps to 0000h-07FFh © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank ...
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... IOC 16h 96h 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh ADRESL 1Eh 9Eh ANSEL 1Fh 9Fh A0h 20h 3Fh 40h EFh F0h Accesses 70h-7Fh 7Fh FFh Bank 1 © 2006 Microchip Technology Inc. ...
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... Unimplemented Legend: – = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO PD ...
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... PSSBD1 PSSBD0 0000 0000 88, 101 — — VR1 VR0 0-00 0000 62, 101 — CMCH 0000 -0-0 58, 101 — — — T1GSS CMSYNC ---0 0-10 59, 101 — — xxxx xxxx 71, 101 GO/DONE ADON 00-0 0000 70, 101 © 2006 Microchip Technology Inc. ...
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... MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. 4: TRISIO3 always reads as ‘1’ since input only pin. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 5 Bit 4 ...
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... P1BSEL P1ASEL ---0 --00 18, 101 — — WPU1 WPU0 --11 -111 34, 101 IOC1 IOC0 --00 0000 34, 101 — — — — — — — — — — — — — — xxxx xxxx 71, 101 ANS1 ANS0 -000 1111 33, 101 © 2006 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 It is recommended, therefore, that only BCF, BSF, ...
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... PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC 128 256 1 : 128 Preliminary R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... IOC register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 R/W-0 (1) — CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary U-0 R/W-0 R/W-0 (1) — TMR2IE TMR1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. DS41302A-page 20 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... P1B function is on GP4/AN3/CIN1-/T1G/P1B 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT bit 0 P1ASEL: P1A Output Pin Select bit 1 = P1A function is on GP5/T1CKI/P1A 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Note 1: PIC12F615/HV615 only. 2: Alternate pin function. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 (1) R/W-0 U-0 U-0 T1GSEL — ...
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... Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE Preliminary INDIRECT ADDRESSING 0x40 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,7 ;all done? NEXT ;no clear next ;yes continue © 2006 Microchip Technology Inc. ...
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... Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in this area are mirrored back into Bank 0 and Bank 1. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 0 IRP Bank Select ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 24 Preliminary © 2006 Microchip Technology Inc. ...
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... PIC MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode. 3. ...
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... These oscillator delays are shown in Table 3-1. Frequency Oscillator Delay 125 kHz to 8 MHz Oscillator Warm-Up Delay (T DC – 20 MHz 2 instruction cycles 32 kHz to 20 MHz 1024 Clock Cycles (OST) (1) Preliminary ) WARM © 2006 Microchip Technology Inc. ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 M © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...
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... Internal signal may be used to provide a clock for external Clock circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. 100 k , <3V ) values EXT Preliminary See Section 11.0 “Special © 2006 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 11-1) for operation of all register bits. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 30 Preliminary © 2006 Microchip Technology Inc. ...
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... Note 1: TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1. ...
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... Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. Note change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. Preliminary © 2006 Microchip Technology Inc. ...
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... Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 U-0 R/W-1 U-0 — ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 IOC4 IOC3 IOC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 WPU1 WPU0 bit Bit is unknown R/W-0 R/W-0 IOC1 IOC0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 4.2.4.2 Figure 4-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: • a general purpose I/O • ...
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... Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/HV615 only. DS41302A-page 36 (1) / Note 1: PIC12F615/HV615 only. (1) Analog Input Mode C1OE Enable C1OE (1) Analog Input Mode GPIO To Timer0 To INT (3) To A/D Converter Preliminary ( Weak GPPU V DD I/O Pin © 2006 Microchip Technology Inc. ...
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... FIGURE 4-3: BLOCK DIAGRAM OF GP3 Data Bus RD TRISIO RD GPIO WR IOC RD IOC ( Interrupt-on- Change R Write ‘0’ to GBIF Note 1: Set has priority over Reset © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PP (1, 2) MCLRE Reset From other GP<5:4, 2:0> pins Preliminary V DD Weak MCLRE Input ...
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... CLK Modes GPPU Oscillator Circuit OSC1 CLKOUT Enable F /4 OSC CLKOUT Enable D Q INTOSC/ (2) RC/ CLKOUT Enable Analog Input Mode From other GP<5, 3:0> pins RD GPIO To T1G (5) To A/D Converter Preliminary ( Weak V DD I/O Pin © 2006 Microchip Technology Inc. ...
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... FIGURE 4-5: BLOCK DIAGRAM OF GP5 ( Interrupt-on- Change R Write ‘0’ to GBIF Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note 1: Alternate pin function. 2: PIC12F615/HV615 only. INTOSC Mode Data Bus WPU ...
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... CMCH 0000 -0-0 0000 -0-0 GPIF 0000 0000 0000 0000 IOC0 --00 0000 --00 0000 PS0 1111 1111 1111 1111 GP0 --x0 x000 --u0 u000 TRISIO0 --11 1111 --11 1111 WPU0 --11 -111 --11 -111 — ---- 0--- CCP1M0 ---- 0000 P1ASEL ---0 --00 © 2006 Microchip Technology Inc. ...
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... WDTE Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 15.0 “Electrical Specifications”. Preliminary © 2006 Microchip Technology Inc. TIMER0) ;Clear WDT and ;prescaler ; ;Mask TMR0 select and ...
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... TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 44 Preliminary © 2006 Microchip Technology Inc. ...
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... When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source ...
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... Synchronize does not operate while in Sleep. 4: Alternate pin function. 5: PIC12F615/HV615 only. DS41302A-page 46 TMR1ON To Comparator Module Timer1 Clock ( TMR1L 1 (1) T1SYNC 1 Prescaler T1CKPS<1:0> TMR1CS F OSC OSC 0 Internal T1GSEL Clock T1ACS Preliminary TMR1GE T1GINV Synchronized clock input (3) Synchronize det COUT 0 (2) T1GSS © 2006 Microchip Technology Inc. ...
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... Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized ...
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... This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. Preliminary © 2006 Microchip Technology Inc. to utilize OSC ...
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... Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-0 R/W-0 R/W-0 T1CKPS0 ...
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... Resets P1ASEL ---0 --00 ---0 --00 CMCH 0000 -0-0 0000 -0-0 CMSYNC ---0 0-10 ---0 0-10 GPIF 0000 000x 0000 000x TMR1IE -00- 0-00 -00- 0-00 TMR1IF -00- 0-00 -00- 0-00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 0000 uuuu uuuu © 2006 Microchip Technology Inc. ...
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... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... T2CKPS0 bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets GPIF 0000 0000 0000 0000 (1) TMR1IE -00- 0-00 -00- 0-00 (1) TMR1IF -00- 0-00 -00- 0-00 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 © 2006 Microchip Technology Inc. ...
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... REF MUX CV REF 1 CMV REN Note © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 than the analog voltage at V parator is a digital low level. When the analog voltage greater than the analog voltage output of the comparator is a digital high level. FIGURE 8-1:SINGLE COMPARATOR V + ...
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... The analog SS and the 2: Analog levels on any pin defined as a dig- DD ital input, may cause the input buffer to consume more current than is specified. is recom 0. LEAKAGE V 0.6V T ±500 Preliminary IC To Comparator © 2006 Microchip Technology Inc. ...
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... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 8.3.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register ...
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... Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags comparator interrupts. Preliminary © 2006 Microchip Technology Inc. reset by software reset by software invalid output from the before enabling ...
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... INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.7 Effects of a Reset A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Preliminary DS41302A-page 57 ...
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... Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corresponding port TRIS bit = 0. DS41302A-page 58 R/W-0 U-0 CMPOL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > CMV - < CMV - > CMV - < CMV - IN IN (1) output REF Preliminary R/W-0 U-0 R/W-0 CMR — CMCH bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-2. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 8.9 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register ...
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... REF drain of the voltage reference peripheral. Preliminary SS module current. REF derived and DD output changes with fluctuations in REF , with DD or fixed REF voltage divider REF voltage for use by the Compar- REF © 2006 Microchip Technology Inc. ...
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... COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CMVREN (1) CV REF To Comparators and ADC Module FixedRef To Comparators and ADC Module Note 1: Care should be taken to ensure CV Section 15.0 “Electrical Specifications” for more detail. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 16 Stages Analog MUX 15 0 (1) VR<3:0> 0.6V ...
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... Bit is cleared (1, 2) input of the Comparator REF input of the Comparator REF (2) Value Selection bits (0 REF = (VR<3:0>/24 (VR<3:0>/32 circuit is powered down and does not contribute to I REF Preliminary R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown VR<3:0> 15) current. DD © 2006 Microchip Technology Inc. ...
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... Hysteresis) Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Figure 8-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis ...
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... CMCH 0000 -000 0000 -000 CMSYNC 0000 0000 0000 0000 GPIF 0000 000x 0000 000x TMR1IE -00- 0-00 -00- 0-00 TMR1IF -00- 0-00 -00- 0-00 GP0 --xx xxxx --uu uuuu TRISIO0 --11 1111 --11 1111 VR0 0-00 0000 0-00 0000 © 2006 Microchip Technology Inc. ...
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... Sleep. Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM (+3 INTERNAL) GP0/AN0 GP1/AN1/V REF GP2/AN2 GP4/AN3 CV REF 0.6V Reference 1.2V Reference © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 (ADC) allows V DD VCFG = 0 V REF VCFG = 1 000 001 010 ...
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... Section 15.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC clock adversely affect the ADC result. Preliminary © 2006 Microchip Technology Inc external voltage DD periods AD specification AD , any changes in the RC frequency, ...
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... Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 9.1.5 “Interrupts” for more information. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V ...
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... ADC timing requirements are met. See Section 10.0 “Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Mod- ule (PIC12F615/HV615 only)” for more information. Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 RC clock source is selected, the RC © 2006 Microchip Technology Inc. ...
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... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 9.3 “A/D Requirements”. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ...
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... If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient. DS41302A-page 70 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R-x R-x R-x ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ...
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... R ln(1/2047 10k ln(0.0004885) 50°C- 25°C 0.05µ /° has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD Preliminary 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED © 2006 Microchip Technology Inc. ...
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... R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h 003h 002h 001h 000h REF © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 V DD Sampling Switch Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range ...
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... Resets ADON 00-0 0000 00-0 0000 ANS0 -000 1111 -000 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GP0 --x0 x000 --x0 x000 GPIF 0000 0000 0000 0000 (1) TMR1IE -00- 0-00 -00- 0-00 (1) TMR1IF -00- 0-00 -00- 0-00 TRISIO0 --11 1111 --11 1111 © 2006 Microchip Technology Inc. ...
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... PWM mode; P1A active-high; P1B active-high 1101 = PWM mode; P1A active-high; P1B active-low 1110 = PWM mode; P1A active-low; P1B active-high 1111 = PWM mode; P1A active-low; P1B active-low © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle ...
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... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L Preliminary of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2006 Microchip Technology Inc. ...
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... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 ...
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... CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. Preliminary the match condition by © 2006 Microchip Technology Inc. ...
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... TMR2 Timer2 Module Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 ...
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... DS41302A-page 80 The PWM output (Figure 10-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 10-4: Period Pulse Width TMR2 = 0 CCP1 TRIS ), or OSC Preliminary CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPRxL:CCPxCON<5:4> © 2006 Microchip Technology Inc. ...
Page 83
... PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 EQUATION 10-2: Pulse Width EQUATION 10-3: OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation ...
Page 84
... T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clear- ing the associated TRIS bit. Preliminary © 2006 Microchip Technology Inc. ...
Page 85
... ECCP Mode Single Half-Bridge Note 1: Pulse Steering enables outputs in Single mode. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...
Page 86
... P1C Inactive OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.5 “Programmable Dead-Band Delay mode”). P1D Modulated DS41302A-page 84 Pulse 0 Width Period (1) (1) Delay Delay Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2006 Microchip Technology Inc. PR2+1 PR2+1 ...
Page 87
... Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit P1A P1B © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. ...
Page 88
... Output mode and complete a full PWM cycle before configuring the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41302A-page 86 Preliminary © 2006 Microchip Technology Inc. ...
Page 89
... From Comparator 001 000 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state ...
Page 90
... PWM signal will always restart at the beginning of the next PWM period. DS41302A-page 88 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) condition Preliminary R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 91
... ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 10-12: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Period Shutdown Shutdown Event Occurs ...
Page 92
... P1B ( Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high OSC V+ FET Driver P1A Load FET Driver P1B V- Preliminary EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period Period td (1) ( © 2006 Microchip Technology Inc. ...
Page 93
... TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the PWM. Note 1: For PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 94
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 92 Preliminary © 2006 Microchip Technology Inc. ...
Page 95
... The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 11-1). © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 11.1 Configuration Bits The Configuration bits can be programmed (read as ‘ ...
Page 96
... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41302A-page 94 — — (3) PWRTE WDTE FOSC2 P = Programmable’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary (1) (1) — BOREN1 BOREN0 bit 8 FOSC1 FOSC0 bit Unimplemented bit, read as ‘0’ Bit is unknown DD © 2006 Microchip Technology Inc. ...
Page 97
... Ripple Counter RC OSC Note 1: Refer to the Configuration Word register (Register 11-1). © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” ...
Page 98
... MCLR pin rather than pulling this pin directly to V Preliminary RECOMMENDED MCLR CIRCUIT DD ® PIC R1 MCU greater) R2 MCLR 100 needed with capacitor) C1 0.1 F (optional, not critical) for details (Section 15.0 at the MCLR SS should be used when . SS © 2006 Microchip Technology Inc. ...
Page 99
... DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 If V drops below V DD running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once V rises above V BOR 64 ms Reset ...
Page 100
... Bit 1 — — — POR Preliminary may have gone too DD Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC — — Value on Value on Bit 0 all other POR, BOR (1) Resets BOR ---- --qq ---- --uu C 0001 1xxx 000q quuu © 2006 Microchip Technology Inc. ...
Page 101
... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 T PWRT T PWRT T PWRT Preliminary T OST T OST ) DD T OST ...
Page 102
... Preliminary © 2006 Microchip Technology Inc. Interrupt WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu ---u uuuu (2) uuuu uuuu ...
Page 103
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 11-6 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 MCLR Reset WDT Reset (1) ...
Page 104
... DS41302A-page 102 Program Status Counter Register 000h 0001 1xxx 000h 000u uuuu 000h 0001 0uuu 000h 0000 uuuu uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu Preliminary © 2006 Microchip Technology Inc. PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu ...
Page 105
... Comparator Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • Enhanced CCP Interrupt © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 11-8) ...
Page 106
... Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 11.7.1 “Wake-up from Sleep”. Preliminary (1) Wake-up (If in Sleep mode) Interrupt to CPU © 2006 Microchip Technology Inc. ...
Page 107
... PIR1 — ADIF CCP1IF (1) (1) PIE1 — ADIE CCP1IE Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC12F615/HV615 only. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 (1) (2) Interrupt Latency Inst ( — ...
Page 108
... The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. as clear The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out. Preliminary © 2006 Microchip Technology Inc. ...
Page 109
... Bit 5 OPTION_REG GPPU INTEDG T0CS CONFIG IOSCFS CP MCLRE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 11-1 for operation of all Configuration Word register bits. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 1 0 8-bit Prescaler PSA PS<2:0> 0 PSA Bit 4 ...
Page 110
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 11-9 for more details. Preliminary © 2006 Microchip Technology Inc. ...
Page 111
... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 OST (2) T (3) ...
Page 112
... Stack Program Memory For more information, see “MPLAB Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). /GP3 PP must be above Memory Preliminary Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh ® ICD 2 In-Circuit © 2006 Microchip Technology Inc. ...
Page 113
... See Figure 12-1 for voltage regulator schematic. FIGURE 12-1: VOLTAGE REGULATOR V UNREG R I SER SUPPLY I SHUNT C Feedback BYPASS Device © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V and SER defined by Equation 12- EQUATION 12-1: supply current R ...
Page 114
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 112 Preliminary © 2006 Microchip Technology Inc. ...
Page 115
... For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended conse- quence of clearing the condition that set the GPIF flag. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 TABLE 13-1: OPCODE FIELD ...
Page 116
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2006 Microchip Technology Inc. ...
Page 117
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 BCF Syntax: k Operands: Operation: Status Affected: ...
Page 118
... Decrement f [ label ] DECF f 127 d [0,1] ( (destination) Z Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2006 Microchip Technology Inc. ...
Page 119
... Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 INCFSZ Syntax: Operands: Operation: Status Affected: Description: ...
Page 120
... Cycles: Example: Preliminary Move label ] MOVWF 127 (W) (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2006 Microchip Technology Inc. ...
Page 121
... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 RETLW Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: TABLE DONE RETURN Syntax: Operands: ...
Page 122
... The processor is put into Sleep mode with the oscillator stopped. Subtract W from literal [ label ] SUBLW 255 k - (W) W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition W<3:0> k<3:0> W<3:0> k<3:0> © 2006 Microchip Technology Inc. ...
Page 123
... Operation: (W) .XOR Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 XORWF Syntax: Operands: Operation: Status Affected: Description: f<3:0> f<3:0> Preliminary Exclusive OR W with f ...
Page 124
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 122 Preliminary © 2006 Microchip Technology Inc. ...
Page 125
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 126
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2006 Microchip Technology Inc. ...
Page 127
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 128
... Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary ® L security ICs, CAN ® ® battery management, SEEVAL © 2006 Microchip Technology Inc. ...
Page 129
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ........................................................................... -0. ...
Page 130
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41302A-page 128 8 10 Frequency (MHz Frequency (MHz) Preliminary 20 20 © 2006 Microchip Technology Inc. ...
Page 131
... Note 1: This is the limit to which User defined. Voltage across the shunt should not exceet 5V. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† Max Units 2.0 — ...
Page 132
... OSC LP Oscillator mode MHz OSC XT Oscillator mode MHz OSC XT Oscillator mode MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode MHz OSC INTOSC mode MHz OSC INTOSC mode MHz OSC (3) EXTRC mode MHz OSC HS Oscillator mode © 2006 Microchip Technology Inc. ...
Page 133
... Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 -40°C T ...
Page 134
... Conditions Note WDT, BOR, Comparators, V and REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , both comparators enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2006 Microchip Technology Inc. ...
Page 135
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) ...
Page 136
... A T +125°C for extended A Units Conditions pF In XT, HS and LP modes when external clock is used to drive OSC1 pF E/W -40°C T +85°C A E/W +85°C T +125° Minimum operating MIN voltage V ms Year Provided no other specifications are violated © 2006 Microchip Technology Inc. ...
Page 137
... TH07 P Derated Power DER * These parameters are characterized but not tested. Note current to run the chip alone without driving any load on the output pins. DD © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 +125°C Typ Units 84.6* C/W 8-pin PDIP package 163* C/W ...
Page 138
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-3: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output DS41302A-page 136 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance L Preliminary © 2006 Microchip Technology Inc. ...
Page 139
... Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Q1 ...
Page 140
... OSC MHz V = 3.5V, 25°C DD MHz 2.5V V 5.5V, DD 0°C T +85°C A MHz 2.0V V 5.5V, DD -40°C T +85°C (Ind.), A -40°C T +125°C (Ext 2.0V, -40°C to +85° 3.0V, -40°C to +85° 5.0V, -40°C to +85°C DD © 2006 Microchip Technology Inc. ...
Page 141
... These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Fetch Read Q1 Q2 OS11 OS20 ...
Page 142
... FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41302A-page 140 BOR 37 33* Preliminary 31 34 HYST (Device not in Brown-out Reset) © 2006 Microchip Technology Inc. ...
Page 143
... OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 F and 0.01 F values in parallel are recommended. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 +125°C Min Typ† Max Units 2 — — ...
Page 144
... N = prescale value (2, 4, ..., 256) — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value ( — — ns 32.768 — kHz — — Timers in Sync OSC mode © 2006 Microchip Technology Inc. ...
Page 145
... CCP1 Input Period * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 CC01 CC02 CC03 +125° ...
Page 146
... Preliminary Max Units Comments 1.5)/ – 1 — dB 600 ns (NOTE 1) 1000 — 1.5)/ mV. DD Units Comments V Low Range (VRR = 1) V High Range (VRR = 0) LSb Low Range (VRR = 1) LSb High Range (VRR = 0) s -40°C T +125°C A Units Comments © 2006 Microchip Technology Inc. ...
Page 147
... V REF 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Standard Operating Conditions (unless otherwise stated) Operating temperature Min ...
Page 148
... — — If the A/D clock source is selected as OSC CY RC, a time of T A/D clock starts. This allows the SLEEP instruction to be executed. CY Preliminary Conditions -based, V 3.0V REF (3) -based, V full range REF = 2. 5. added before the CY cycle. © 2006 Microchip Technology Inc. ...
Page 149
... AD134 ( OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the ...
Page 150
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 148 Preliminary © 2006 Microchip Technology Inc. ...
Page 151
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Preliminary DS41302A-page 149 ...
Page 152
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 150 Preliminary © 2006 Microchip Technology Inc. ...
Page 153
... Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Example ...
Page 154
... L p MILLIMETERS MIN NOM MAX 8 2.54 3.56 3.94 4.32 2.92 3.30 3.68 0.38 7.62 7.94 8.26 6.10 6.35 6.60 9.14 9.46 9.78 3.18 3.30 3.43 0.20 0.29 0.38 1.14 1.46 1.78 0.36 0.46 0.56 7.87 9.40 10. © 2006 Microchip Technology Inc. ...
Page 155
... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 ...
Page 156
... BSC – – 1.20 0.80 1.00 1.05 0.05 – 0.15 6.40 BSC 4.30 4.40 4.50 2.90 3.00 3.10 0.45 0.60 0.75 0° – 8° 0.09 – 0.20 0.19 – 0.30 12° REF 12° REF Revised 7-25-06 © 2006 Microchip Technology Inc. ...
Page 157
... BSC e A 0.80 0.90 A1 0.00 0.02 0.20 REF A3 4.00 BSC D E2 0.00 2.20 E 4.00 BSC 3.00 D2 0.00 0.25 0. 0.30 0.55 K 0.20 — Microchip Technology Drawing No. C04–131, Sept. 8, 2006 Preliminary NOTE 1 MAX 1.00 0.05 2.80 3.60 0.35 0.65 — DS41302A-page 155 ...
Page 158
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 156 Preliminary © 2006 Microchip Technology Inc. ...
Page 159
... APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 APPENDIX B: This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices. B.1 PIC12F675 to PIC12F609/615/ 12HV609/615 TABLE B-1: FEATURE COMPARISON Feature ...
Page 160
... PIC12F609/615/12HV609/615 NOTES: DS41302A-page 158 Preliminary © 2006 Microchip Technology Inc. ...
Page 161
... GP0 and GP1 Pins...................................................... 35 GP2 Pins..................................................................... 36 GP3 Pin....................................................................... 37 GP4 Pin....................................................................... 38 GP5 Pin....................................................................... 39 In-Circuit Serial Programming Connections.............. 110 Interrupt Logic ........................................................... 104 MCLR Circuit............................................................... 96 On-Chip Reset Circuit ................................................. 95 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 PIC16F609/16HV609 ................................................... 5 PIC16F615/16HV615 ................................................... 6 PWM (Enhanced) ....................................................... 83 Resonator Operation .................................................. 27 Timer1 .................................................................. 45, 46 Timer2 ........................................................................ 51 TMR0/WDT Prescaler ................................................ 41 Watchdog Timer ...
Page 162
... IORWF...................................................................... 117 MOVF ....................................................................... 118 MOVLW .................................................................... 118 MOVWF .................................................................... 118 NOP .......................................................................... 118 RETFIE ..................................................................... 119 RETLW ..................................................................... 119 RETURN................................................................... 119 RLF ........................................................................... 120 RRF .......................................................................... 120 SLEEP ...................................................................... 120 SUBLW ..................................................................... 120 SUBWF..................................................................... 121 SWAPF ..................................................................... 121 XORLW .................................................................... 121 XORWF .................................................................... 121 Summary Table ........................................................ 114 Preliminary © 2006 Microchip Technology Inc. ...
Page 163
... Oscillator Specifications .................................................... 137 Oscillator Start-up Timer (OST) Specifications............................................................ 141 OSCTUNE Register ............................................................ 29 P P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/PWM (ECCP) ................................ 83 Packaging ......................................................................... 151 © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 Marking..................................................................... 151 PDIP Details ............................................................. 152 PCL and PCLATH............................................................... 22 Stack........................................................................... 22 PCON Register ............................................................. 20, 98 PICSTART Plus Development Programmer..................... 126 PIE1 Register ...
Page 164
... Voltage Reference (CV REF Voltage References Associated registers ................................................... 64 VP6 Stabilization ........................................................ ADC Reference Voltage REF EE W Wake-up Using Interrupts ................................................. 108 Watchdog Timer (WDT).................................................... 106 Associated registers ................................................. 107 Specifications ........................................................... 141 WPU Register ..................................................................... 34 WWW Address ................................................................. 163 WWW, On-Line Support ....................................................... 4 Preliminary © 2006 Microchip Technology Inc. ) ...
Page 165
... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. PIC12F609/615/12HV609/615 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
Page 166
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41302A-page 164 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41302A Preliminary © 2006 Microchip Technology Inc. ...
Page 167
... Microchip Technology Inc. PIC12F609/615/12HV609/615 XXX Examples: Pattern a) PIC12F615-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F615-I/SN = Industrial Temp., SOIC package, 20 MHz (1) (1) , PIC12HV609, PIC12HV609T , (1)) (1) , PIC12HV615, PIC12HV615T (Industrial) (Extended) Note 1: Preliminary . tape and reel TSSOP and SOIC packages only. DS41302A-page 165 ...
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