PIC12HV615-I/SN Microchip Technology, PIC12HV615-I/SN Datasheet - Page 98
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PIC12HV615-I/SN
Manufacturer Part Number
PIC12HV615-I/SN
Description
IC PIC MCU FLASH 1KX14 8SOIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F609T-ISN.pdf
(26 pages)
4.PIC16F616T-ISL.pdf
(4 pages)
5.PIC16F616T-ISL.pdf
(8 pages)
6.PIC12F615-ESN.pdf
(168 pages)
Specifications of PIC12HV615-I/SN
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-SOIC (3.9mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12H
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS-232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12HV615-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC12F609/615/12HV609/615
11.3.1
The on-chip POR circuit holds the chip in Reset until
V
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to V
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
V
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until V
reaches V
(BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
11.3.2
PIC12F609/615/12HV609/615 has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to V
Figure 11-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the GP3/MCLR pin
becomes an external Reset input. In this mode, the
GP3/MCLR pin has a weak pull-up to V
DS41302A-page 96
DD
DD
Note:
has reached a high enough level for proper
is required. See Section 15.0 “Electrical
BOR
DD
POWER-ON RESET (POR)
The POR circuit does not produce an
internal Reset when V
enable the POR, V
a minimum of 100 s.
MCLR
. The use of an RC network, as shown in
(see Section 11.3.4 “Brown-out Reset
DD
DD
must reach Vss for
declines. To re-
DD
.
DD
. This
Preliminary
DD
FIGURE 11-2:
11.3.3
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from an internal
RC oscillator. For more information, see Section 3.4
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
V
PWRTE, can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Reset is
enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
• V
• Temperature variation
• Process variation
See
“Electrical Specifications”).
DD
Note:
DD
to rise to an acceptable level. A Configuration bit,
(optional)
SW1
DC
variation
POWER-UP TIMER (PWRT)
Voltage spikes below V
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to V
parameters
V
DD
R1
1 k
C1
0.1 F
(optional, not critical)
needed with capacitor)
or greater)
RECOMMENDED
CIRCUIT
© 2006 Microchip Technology Inc.
100
for
R2
should be used when
details
SS
MCLR
at the MCLR
(Section 15.0
MCU
PIC
MCLR
®
SS
.