PIC18LF13K50-I/MQ Microchip Technology, PIC18LF13K50-I/MQ Datasheet - Page 36

• Manufacturer Part Number: PIC18LF13K50-I/MQ
• Description: IC PIC MCU FLASH 512KX8 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K50-I/MQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: PIC18
• No. Of I/o's: 15
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK50/PIC18LF1XK50
FIGURE 3-5:
DS41350E-page 36
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank
BSR<3:0>
= 0000
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 0001
= 1111
DATA MEMORY MAP FOR PIC18F13K50/PIC18LF13K50 DEVICES
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Data Memory Map
Access RAM
Read 00h
(DPRAM)
Read 00h
Unused
Unused
SFR
Unused
GPR
GPR
SFR
(1)
Preliminary
F60h
FFFh
F53h
F5Fh
000h
05Fh
060h
0FFh
100h
1FFh
200h
2FFh
300h
3FFh
400h
4FFh
500h
5FFh
600h
6FFh
700h
7FFh
800h
8FFh
900h
9FFh
A00h
AFFh
B00h
BFFh
C00h
CFFh
D00h
DFFh
E00h
EFFh
F00h
When ‘a’ = 0:
When ‘a’ = 1:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
The BSR specifies the Bank
used by the instruction.
 2010 Microchip Technology Inc.
Access RAM High
Access RAM Low
Access Bank
(SFRs)
FFh
00h
5Fh
60h