AT89LP4052-20XU Atmel, AT89LP4052-20XU Datasheet - Page 58

• Manufacturer Part Number: AT89LP4052-20XU
• Description: IC 8051 MCU FLASH 4K 20TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP4052-20XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Package: 20TSSOP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

23.1
Notes:
58
Command
Program Enable
Chip Erase
Read Status
Load Code Page Buffer
Write Code Page
Read Code Page
Write User Fuses
Read User Fuses
Write Lock Bits
Read Lock Bits
Write User Signature Page
Read User Signature Page
Read Atmel Signature Page
Programming Command Summary
1. Program Enable must be the first command issued after entering into programming mode.
2. Any number of Data bytes from 1 to 32 may be written/read. The internal address is incremented between each byte.
3. Fuse Bit Definitions:
4. Lock Bit Definitions:
5. Atmel Signature Byte:
6. Symbol Key:
AT89LP2052/LP4052
*The AT89LP2052/LP4052 has ISP enabled by default from the factory. However, if ISP is later disabled, the ISP Enable
Fuse must be enabled by using Parallel Programming before entering ISP mode.
When disabling the ISP fuse during ISP, the current ISP session will remain active until RST is brought low.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 0
Bit 1
AT89LP2052:
AT89LP4052:
(4)
(4)
(1)
(2)
(2)
(3)
(3)
ISP Enable*
XTAL Osc Bypass
User Row Programming
System Clock Out
Lock Bit 1
Lock Bit 2
A: Page Address Bit
B: Byte Address Bit
F: Fuse Bit Data
L: Lock Bit Data
x: Don’t Care
(2)
(2)
(2)
(2)(5)
Address 00H = 1EH
Address 00H = 1EH
01H = 25H
02H = FFH
01H = 45H
02H = FFH
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
1010 1010
Preamble
Enable = 0/Disable = 1
Enable = 0/Disable = 1
Enable = 0/Disable = 1
Enable = 0/Disable = 1
Locked = 0/Unlocked = 1
Locked = 0/Unlocked = 1
1010 1100
1000 1010
0110 0000
0101 0001
0101 0000
0011 0000
1110 0001
0110 0001
1110 0100
0110 0100
0101 0010
0011 0010
0011 1000
Opcode
0101 0011
xxxx xxxx
xxxx xxxx
xxxx AAAA
xxxx AAAA
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Addr High
xxxx
xxxB BBBB
AAAB BBBB
AAAB BBBB
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxB BBBB
xxxB BBBB
xxxB BBBB
Addr Low
xxxx
xxxx FFFF
xxxx FFFF
xxxx xxLL
xxxx xxLL
Status Out
Data 0
DataOut 0 ... DataOut n
DataOut 0 ... DataOut n
DataOut 0 ... DataOut n
DataIn 0 ... DataIn n
DataIn 0 ... DataIn n
DataIn 0 ... DataIn n
3547J–MICRO–10/09
Data n