PIC16F628A-I/P Microchip Technology, PIC16F628A-I/P Datasheet - Page 84

• Manufacturer Part Number: PIC16F628A-I/P
• Description: IC MCU FLASH 2KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/P

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Package: 18PDIP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIPACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an OERR error occurred, clear the error by
TABLE 12-7:
DS40044F-page 82
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
clearing enable bit CREN.
PIR1
RCSTA
RCREG USART Receive Data Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
Name
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
CSRC
SPEN
EEIE
Bit 7
EEIF
CMIE
CMIF
Bit 6
RX9
TX9
SREN
TXEN
RCIF
RCIE
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
ADEN
Bit 3
—
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
BRGH
FERR
Bit 2
OERR
TRMT
Bit 1
RX9D
TX9D
Bit 0
© 2007 Microchip Technology Inc.
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
Value on
POR
Value on
all other
Resets