PIC18F44J10-I/P Microchip Technology, PIC18F44J10-I/P Datasheet - Page 5
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F44J10-I/P
Manufacturer Part Number
PIC18F44J10-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
7.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F44J10-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
9. Module: EUSART
2009 Microchip Technology Inc.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by
the module operating in Asynchronous mode.
The actual data is not lost or corrupted; only
unwanted (extra) zero bytes are observed in the
packet.
This situation has only been observed when the
contents of the Transmit Buffer (TXREG) are
transferred to the TSR during the transmission
of a Stop bit. For this to occur, three things must
happen in the same instruction cycle:
• TXREG is written to
• The baud rate counter overflows (at the end of
• A Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double-
buffer capability. Instead, load the TXREG
register when the TRMT bit (TXSTA<1>) is set,
indicating the TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, load TXREG imme-
diately after TXIF is set or wait 1 bit time after
TXIF is set. Both solutions prevent writing
TXREG while a Stop bit is transmitted.
The TXIF bit is set at the beginning of the Stop
bit transmission.
If transmission is intermittent, do one of the
following:
• Wait for the TRMT bit to be set before
• Use a free timer resource to time the baud
Affected Silicon Revisions
A2
the bit period)
TSR)
loading TXREG
period:
1.
2.
Do not load the TXREG when the timer is
about to overflow.
X
Set up the timer to overflow at the end of
the Stop bit.
Start the timer when you load the TXREG.
A3
X
A4
X
PIC18F45J10 FAMILY
10. Module: ECCP (Enhanced PWM)
11. Module: MSSP – I
When switching direction in Full-Bridge PWM
mode, the modulated outputs will switch imme-
diately instead of waiting for the next PWM
cycle. This may generate unexpected short
pulses on the modulated outputs.
Work around
Disable the PWM or set the duty cycle to zero
prior to switching directions.
Affected Silicon Revisions
When configured for I
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these
ways:
• Prior to the I
• Each time the SSPxIF is set, read the
Affected Silicon Revisions
A2
A2
clock stretching feature.
This
(SSPCON2<0>).
SSPBUF before the first rising clock edge of
the next byte being received.
X
X
A3
A3
X
X
is
Receive/Transmit
done
A4
A4
2
X
X
C slave reception, enable the
by
2
C™
2
C slave reception, the
setting
Buffer
DS80494B-page 5
the
register
SEN
bit