PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet
PIC18F6680-I/L
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PIC18F6680-I/L Summary of contents
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... PIC18F6585/8585/6680/8680 Microcontrollers with ECAN Module 2004 Microchip Technology Inc. 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Data Sheet DS30491C ...
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... ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. ...
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... Enhanced Addressable USART module: - Supports RS-232, RS-485 and LIN 1.2 - Programmable wake-up on Start bit - Auto-baud detect • Parallel Slave Port (PSP) module 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Analog Features: • 16-channel, 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate ...
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... Wide operating voltage range (2.0V to 5.5V) • Industrial and Extended temperature ranges Program Memory Data Memory Device # Single-Word SRAM Bytes Instructions (bytes) PIC18F6585 48K 24576 3328 PIC18F6680 64K 32768 3328 PIC18F8585 48K 24576 3328 PIC18F8680 64K 32768 3328 DS30491C-page 2 MSSP ...
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... TQFP RE1/WR 1 RE0/RD 2 RG0/CANTX1 3 RG1/CANTX2 4 RG2/CANRX 5 RG3 6 RG5/MCLR RG4/P1D RF7/SS 11 RF6/AN11/C1IN- 12 RF5/AN10/C1IN+/CV REF 13 RF4/AN9/C2IN- 14 RF3/AN8/C2IN+ 15 RF2/AN7/C1OUT 16 Note 1: CCP2 pin placement depends on CCP2MX setting. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 PIC18F6X8X RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1/PGM 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI RB7/KBI3/PGD 37 RC5/SDO 36 ...
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... PP 17 RG4/P1D 18 N RF7/SS RF6/AN11/C1IN RF5/AN10/C1IN+/CV REF RF4/AN9/C2IN- 24 RF3/AN8/C2IN RF2/AN7/C1OUT Note 1: CCP2 pin placement depends on CCP2MX setting. DS30491C-page Top View PIC18F6X8X RB0/INT0 59 RB1/INT1 58 RB2/INT2 57 RB3/INT3 56 RB4/KBI0 55 RB5/KBI1/PGM 54 RB6/KBI2/PGC N/C 51 OSC2/CLKO/RA6 50 OSC1/CLKI RB7/KBI3/PGD 47 RC5/SDO 46 RC4/SDI/SDA 45 RC3/SCK/SCL 44 RC2/CCP1/P1A 2004 Microchip Technology Inc. ...
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... RF4/AN9/C2IN- 16 RF3/AN8/C2IN+ 17 RF2/AN7/C1OUT 18 (3) RH7/AN15/P1B 19 (3) RH6/AN14/P1C Note 1: PSP is available only in Microcontroller mode. 2: CCP2 pin placement depends on CCP2MX and Processor mode settings. 3: P1B and P1C pin placement depends on ECCPMX setting. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 PIC18F8X8X RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 ...
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... Appendix C: Conversion Considerations ........................................................................................................................................... 470 Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 470 Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 471 Index .................................................................................................................................................................................................. 473 On-Line Support................................................................................................................................................................................. 487 Systems Information and Upgrade Hot Line ...................................................................................................................................... 487 Reader Response .............................................................................................................................................................................. 488 PIC18F6585/8585/6680/8680 Product Identification System ............................................................................................................ 489 DS30491C-page 6 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 DS30491C-page 7 ...
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... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 8 2004 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6585 • PIC18F8585 • PIC18F6680 • PIC18F8680 PIC18F6X8X devices are available in 64-pin TQFP and 68-pin PLCC packages. PIC18F8X8X devices are available in the 80-pin TQFP package. They are differentiated from each other in four ways: 1 ...
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... RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD7/PSP7 :RD0/PSP0 PORTE RE0/RD RE1/WR RE2/CS RE3 RE4 RE5/P1C RE6/P1B (1) RE7/CCP2 PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8/C2IN+ RF4/AN9/C2IN- RF5/AN10/C1IN+/CV REF RF6/AN11/C1IN- RF7/SS PORTG RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 RG4/P1D RG5/MCLR/V PP 10-bit Data EEPROM ADC 2004 Microchip Technology Inc. ...
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... ECCP1 CCP2 Comparator AUSART Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings. 2: P1B and P1C pin placement depends on the ECCPMX setting. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Data Bus<8> Data Latch 8 8 Data RAM (3328 bytes) Address Latch ...
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... In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2004 Microchip Technology Inc. ...
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... PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Pin Buffer Type Type TQFP PORTA is a bidirectional I/O port. ...
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... Interrupt-on-change pin. I/O ST In-circuit debugger and ICSP programming clock. 47 I/O TTL Digital I/O. I/O ST Interrupt-on-change pin. In-circuit debugger and ICSP programming data. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2004 Microchip Technology Inc. ...
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... PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Pin Buffer Type Type TQFP PORTC is a bidirectional I/O port. ...
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... Parallel Slave Port data. I/O TTL External memory address/data 6. 63 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. I/O TTL External memory address/data 7. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2004 Microchip Technology Inc. ...
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... PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Pin Buffer Type Type TQFP PORTE is a bidirectional I/O port. ...
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... Comparator V 14 I/O ST Digital I/O. I Analog Analog input 11. I Analog Comparator 1 input (-) 13 I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description output. REF ) DD 2004 Microchip Technology Inc. ...
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... PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Pin Buffer Type Type TQFP PORTG is a bidirectional I/O port. ...
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... I/O ST Digital I/O. I Analog Analog input 14. I/O ST Alternate CCP1 PWM output C. 19 I/O ST Digital I/O. I Analog Analog input 15. Alternate CCP1 PWM output B. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ( 2004 Microchip Technology Inc. ...
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... PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Pin Buffer Type Type TQFP PORTJ is a bidirectional I/O port ...
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... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 22 2004 Microchip Technology Inc. ...
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... The PIC18F6585/8585/6680/8680 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 FIGURE 2-1: (1) C1 OSC1 XTAL ...
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... I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXX80/XX85 OSC2 ) and capacitor (C ) val- EXT EXT values. The user also needs to EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC18FXX80/XX85 OSC2/CLKO / 100 k EXT C > 20pF EXT 2004 Microchip Technology Inc. ...
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... PLL Enable Phase Comparator OUT 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 2.5 Phase Locked Loop (PLL) A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz ...
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... See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 24.0 “Special Features of the CPU” for configuration register details. PIC18FXX80/XX85 Tosc PLL Sleep T OSC T1OSCEN Enable Oscillator Clock Source Option for other Modules T SCLK Clock Source 2004 Microchip Technology Inc. ...
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... ECIO+SPLL and HS+SPLL modes only. 2: The setting of SCS0 = 1 supersedes SCS1 = 1. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 enabled (PLLEN = 1) and locked (LOCK = 1), else it will be forced clear. When programmed with Configuration Controlled PLL mode, the SCS1 bit will be forced clear. ...
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... XT, LP), then the transition will take place after an oscillator start-up time (T timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes, is shown in Figure 2- SCS OST T OSC has occurred. A OST SCS 2004 Microchip Technology Inc. ...
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... Input Internal System Clock SCS (OSCCON<0>) Program Counter PC 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 If the main oscillator is configured for EC mode with PLL ) plus an active, only the PLL time-out (T OST time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram, indicat- ing the transition from the Timer1 oscillator to the main oscillator for EC with PLL active, is shown in Figure 2-11 ...
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... RC, RCIO, EC and ECIO modes, is shown in Figure 2-12. FIGURE 2-12: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC T1OSI OSC1 Internal System Clock SCS (OSCCON<0>) Program PC Counter Note: RC Oscillator mode assumed. DS30491C-page OSC SCS 2004 Microchip Technology Inc ...
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... BOR). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 switching currents have been removed, Sleep mode achieves the lowest current consumption of the device (only leakage currents) ...
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... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 32 2004 Microchip Technology Inc. ...
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... RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 3-2 ...
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... Function Registers while Table 3-3 shows the Reset conditions for all of the registers. falls below parameter D005 for greater falls below DD rises above DD rises above then will keep DD DD drops below BV while the Power- the Power-up Timer will DD 2004 Microchip Technology Inc. ...
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... Legend unchanged unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h). 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 (2) Power-up PWRTE = 1 + 2ms ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu uuuu (1) uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2004 Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 T PWRT T OST T PWRT T T PWRT T VIA 1 k RESISTOR CASE 1 ...
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... MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL DS30491C-page 50 VIA 1 k RESISTOR PWRT T OST VIA 1 k RESISTOR PWRT T OST T PLL 2004 Microchip Technology Inc. ...
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... The PIC18F6585 and PIC18F8585 48 Kbytes of on-chip Flash memory, while the PIC18F6680 and PIC18F8680 have 64 Kbytes of Flash. This means that PIC18FX585 devices can store inter- nally up to 24,576 single-word instructions and PIC18FX680 devices can store up to 32,768 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... No Access No Access Yes Yes Yes Yes Yes Yes No Access Yes Yes Yes INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18F6680/8680 PC<20:0> 21 Stack Level 1 Stack Level 31 000000h Reset Vector 000018h On-Chip Flash Program Memory 00FFFFh 010000h Read ‘0’ 1FFFFFh 200000h External Program Memory ...
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... External Program Memory 1FFFFFh 1FFFFFh External On-Chip Memory Flash Note 1: PIC18F6585 and PIC18F8585. 2: PIC18F6680 and PIC18F8680. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 U-0 U-0 U-0 — — — — Programmable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
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... The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. stack 2004 Microchip Technology Inc. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-0 R/W-0 (1) — ...
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... Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4- PC+2 Execute INST (PC) Fetch INST (PC+2) GOTO and program branch Internal Phase Clock PC+4 Execute INST (PC+2) Fetch INST (PC+4) 2004 Microchip Technology Inc. ...
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... Instruction 1: MOVLW Instruction 2: GOTO Instruction 3: MOVFF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles ...
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... Table Latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. A description of the table read/table write operation is shown in Section 5.0 “Flash Program Memory”. 2004 Microchip Technology Inc. ...
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... BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 “Access Bank” provides a detailed description of the Access RAM. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 4.9.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi- rectly ...
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... Access RAM low 5Fh 60h Access RAM high (SFRs) FFh When the BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). 2004 Microchip Technology Inc. ...
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... FE2h FSR1H FC2h FE1h FSR1L FC1h FE0h BSR FC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Name Address Name (3) INDF2 FBFh CCPR1H (3) POSTINC2 FBEh CCPR1L ...
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... F11h RXF4SIDL F10h RXF4SIDH F0Fh RXF3EIDL F0Eh RXF3EIDH F0Dh RXF3SIDL F0Ch RXF3SIDH F0Bh RXF2EIDL F0Ah RXF2EIDH F09h RXF2SIDL F08h RXF2SIDH F07h RXF1EIDL F06h RXF1EIDH F05h RXF1SIDL F04h RXF1SIDH F03h RXF0EIDL F02h RXF0EIDH F01h RXF0SIDL F00h RXF0SIDH 2004 Microchip Technology Inc. ...
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... EC2h (1) EE1h — EC1h (1) EE0h — EC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Name Address Name (1) (1) — EBFh — (1) (1) — EBEh — ...
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... E11h — (1) E10h — (1) E0Fh — (1) E0Eh — (1) E0Dh — (1) E0Ch — (1) E0Bh — (1) E0Ah — (1) E09h — (1) E08h — (1) E07h — (1) E06h — (1) E05h — (1) E04h — (1) E03h — (1) E02h — (1) E01h — (1) E00h — 2004 Microchip Technology Inc. ...
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... DE2h RXFBCON2 DC2h DE1h RXFBCON1 DC1h DE0h RXFBCON0 DC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Name Address Name (1) (1) — DBFh — (1) (1) — ...
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... RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. DS30491C-page 66 Name Address Name Address Name 2004 Microchip Technology Inc. ...
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... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... CCP2M1 CCP2M0 --00 0000 38, 172 PSSBD1 PSSBD0 0000 0000 38, 172 CVR1 CVR0 0000 0000 38, 265 CM1 CM0 0000 0000 38, 259 xxxx xxxx 38, 164 xxxx xxxx 38, 164 TMR3CS TMR3ON 0000 0000 38, 164 — — 0000 ---- 38, 153 2004 Microchip Technology Inc. ...
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... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 ...
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... RXB0D70 xxxx xxxx 40, 230 RXB0D61 RXB0D60 xxxx xxxx 40, 230 RXB0D51 RXB0D50 xxxx xxxx 40, 230 RXB0D41 RXB0D40 xxxx xxxx 40, 230 RXB0D31 RXB0D30 xxxx xxxx 40, 230 RXB0D21 RXB0D20 xxxx xxxx 40, 230 RXB0D11 RXB0D10 xxxx xxxx 40, 230 RXB0D01 RXB0D00 xxxx xxxx 40, 230 2004 Microchip Technology Inc. ...
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... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 ...
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... EID17 EID16 xx-x 0-xx 43, 230 SID4 SID3 xxxx xxxx 43, 230 EID1 EID0 xxxx xxxx 43, 230 EID9 EID8 xxxx xxxx 43, 230 EID17 EID16 xx-x 0-xx 43, 230 SID4 SID3 xxxx xxxx 43, 230 EID1 EID0 xxxx xxxx 47, 230 2004 Microchip Technology Inc. ...
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... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 ...
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... EID16 xxxx x-xx 44, 230 SID4 SID3 xxxx xxxx 44, 230 FILHIT1/ FILHIT0/ 0000 0000 44, 230 TXPRI1 TXPRI0 B4D71 B4D70 xxxx xxxx 44, 230 B4D61 B4D60 xxxx xxxx 44, 230 B4D51 B4D50 xxxx xxxx 44, 230 B4D41 B4D40 xxxx xxxx 44, 230 2004 Microchip Technology Inc. ...
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... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 ...
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... FIL12_1 FIL12_0 0000 0000 46, 230 FIL8_1 FIL8_0 0000 0000 46, 230 FIL4_1 FIL4_0 0000 0101 46, 230 FIL0_1 FIL0_0 0101 0000 46, 230 DFLC1 DFLC0 ---0 0000 46, 230 RXF9EN RXF8EN 0000 0000 46, 230 RXF1EN RXF0EN 0011 1111 47, 230 2004 Microchip Technology Inc. ...
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... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 ...
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... Registers” provides a description of indirect address- ing which allows linear addressing of the entire RAM space. Direct Addressing (3) From Opcode 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 2004 Microchip Technology Inc. ...
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... FSR register being the address of the data instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 the data from FSR1H:FSR1L ...
Page 82
... FIGURE 4-10: INDIRECT ADDRESSING 11 Location Select Note 1: For register file map detail, see Table 4-2. DS30491C-page 80 0h RAM Address 0FFFh 12 File Address = Access of an Indirect Addressing Register File FSR Indirect Addressing FSR Register 0 0000h Data (1) Memory 0FFFh 2004 Microchip Technology Inc. ...
Page 83
... Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). ...
Page 84
... POR was set to ‘1’ by software immediately after POR). U-0 U-0 R/W-1 R/W-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 85
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 86
... The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. 2004 Microchip Technology Inc. TABLAT ...
Page 87
... Initiates an EEPROM read. (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit W = Writable bit ‘1’ = Bit is set 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-0 R/W-x — FREE WRERR U = Unimplemented bit, read as ‘ ...
Page 88
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> TBLPTRL 0 2004 Microchip Technology Inc. ...
Page 89
... LSB TBLRD*+ MOVF TABLAT, W MOVWF MSB 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 90
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts 2004 Microchip Technology Inc. ...
Page 91
... TABLE WRITES TO FLASH PROGRAM MEMORY 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 the holding registers are written. At the end of updating eight registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the inter- nal Flash ...
Page 92
... Load TBLPTR with the base ; address of the memory block ; read into TABLAT, and inc ; get data ; store data ; done? ; repeat ; point to buffer ; update buffer word 2004 Microchip Technology Inc. ...
Page 93
... BSF INTCON, GIE DECFSZ COUNTER_HI BRA PROGRAM_LOOP BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 ; load TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ...
Page 94
... RBIF 0000 0000 0000 0000 — — RD xx-0 x000 uu-0 u000 CCP2IP -1-1 1111 -1-1 1111 CCP2IF -0-0 0000 -0-0 0000 CCP2IE -0-0 0000 -0-0 0000 2004 Microchip Technology Inc. ...
Page 95
... For a more complete discussion of the operating modes that use the external memory interface, refer to Section 4.1.1 “PIC18F8X8X Program Modes”. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 6.1 Program Memory Modes and the External Memory Interface As previously noted, PIC18F8X8X controllers are capable of operating in any one of four program mem- ory modes using combinations of on-chip and external program memory ...
Page 96
... The MEMCON register is held in Reset in Microcontroller mode. DS30491C-page 94 U-0 R/W-0 R/W-0 U-0 — WAIT1 WAIT0 — ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-0 R/W-0 — WM1 WM0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 97
... Input/Output or System Bus Lower Byte Enable (LB) Control pin RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 When the device is executing out of internal memory (with EBDIS = 0) in Microprocessor with Boot Block mode or Extended Microcontroller mode, the control sig- nals will be in inactive. They will state where the AD< ...
Page 98
... BYTE WRITE MODE Figure 6-1 shows an example of 16-bit Byte Write mode for PIC18F8X8X devices. D<7:0> (MSB) A<19:0> 373 A<x:0> D<15:8> D<7:0> CE (1) 373 OE WR (LSB) A<x:0> D<7:0> D<7:0> Address Bus Data Bus Control Lines 2004 Microchip Technology Inc. ...
Page 99
... WORD WRITE MODE EXAMPLE PIC18F8X8X AD<7:0> AD<15:8> ALE A<19:16> WRH Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 A<20:1> 373 D<15:0> 373 JEDEC Word A<x:0> EPROM Memory D<15:0> ...
Page 100
... WRL BA0 Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”. DS30491C-page 98 A<20:1> 373 373 A<20:1> A<x:1> JEDEC Word SRAM Memory D<15:0> D<15:0> Address Bus Data Bus Control Lines 2004 Microchip Technology Inc. ...
Page 101
... FIGURE 6-4: EXTERNAL PROGRAM MEMORY BUS TIMING (16-BIT MODE Apparent Q Actual A<19:16> 0h 3AABh AD<15:0> BA0 ALE OE WRH ‘1’ WRL ‘1’ Opcode Fetch MOVLW 55h from 007556h 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 0E55h CF33h Table Read of 92h from 199E67h ...
Page 102
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 100 2004 Microchip Technology Inc. ...
Page 103
... The write time will vary with voltage and temperature as well as from chip to chip. Please refer to parameter D122 (Electrical Characteristics, Section 27.0 “Electrical Characteristics”) for exact limits. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 7.1 EEADRH:EEADR The address register pair, EEADRH:EEADR, can address maximum of 1024 bytes of data EEPROM ...
Page 104
... R = Readable bit W = Writable bit ‘1’ = Bit is set DS30491C-page 102 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN U = Unimplemented bit, read as ‘0’ Settable bit ‘0’ = Bit is cleared R/S-0 R/S bit Value after erase x = Bit is unknown 2004 Microchip Technology Inc. ...
Page 105
... INTCON, GIE . . . BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 (EECON1<6>) (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation). ...
Page 106
... Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; ; ; Disable writes ; Enable interrupts 2004 Microchip Technology Inc. ...
Page 107
... PIR2 — CMIF — PIE2 — CMIE — Legend unknown unchanged reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF — ...
Page 108
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 106 2004 Microchip Technology Inc. ...
Page 109
... Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 8.2 Operation Example 8-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
Page 110
... WREG ; ADDWFC RES3 ; ; BTFSS ARG2H ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L SUBWF RES2 ; MOVF ARG1H SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L SUBWF RES2 ; MOVF ARG2H SUBWFB RES3 ; CONT_CODE : 2004 Microchip Technology Inc. ...
Page 111
... Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 112
... INT1IP INT2IF INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE GIEL/PEIE RBIP GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2004 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h ...
Page 113
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit ...
Page 114
... DS30491C-page 112 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 115
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 ...
Page 116
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2004 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 117
... Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-0 R/W-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 118
... DS30491C-page 116 R/W-0 R/W-0 R/W-0 R/W-0 (1) ERRIF TXB2IF/ TXB1IF TXB0IF TXBnIF (1) (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 (1) RXB1IF/ RXB0IF/ RXBnIF FIFOWMIF bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 119
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 ADIE RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 120
... R = Readable bit - n = Value at POR DS30491C-page 118 U-0 R/W-0 R/W-0 R/W-0 — EEIE BCLIE LVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2004 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 121
... When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 R/W-0 (1) ERRIE ...
Page 122
... R = Readable bit - n = Value at POR DS30491C-page 120 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 123
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-1 R/W-1 — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 124
... Value at POR DS30491C-page 122 R/W-1 R/W-1 R/W-1 R/W-1 (1) ERRIP TXB2IP/ TXB1IP TXB0IP TXBnIP (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 (1) RXB1IP/ RXB0IP/ RXBnIP FIFOWMIP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 125
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-4. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 U-0 R/W-1 R-1 — — ...
Page 126
... Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS 2004 Microchip Technology Inc. ...
Page 127
... Q WR LAT + WR Port CK Data Latch Data Bus RD Port 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 10.1 PORTA, TRISA and LATA Registers PORTA is a 7-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 128
... I/O pins have protection diodes to V and Data Latch TRIS Latch Q and BLOCK DIAGRAM OF RA4/T0CKI PIN (1) I/O pin N Data Latch Schmitt CK Q Trigger TRIS Latch Input Buffer and (1) N I/O pin V SS TTL Input Buffer D EN 2004 Microchip Technology Inc. ...
Page 129
... PORTA Data Direction Register ADCON1 — — VCFG1 VCFG0 PCFG3 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output or analog input. Input/output or analog input. Input/output or analog input or V REF ...
Page 130
... Q D From other EN RB7:RB4 pins RB7:RB5 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc Weak P Pull-up (1) I/O pin ST Buffer Q1 RD PORTB ...
Page 131
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 V DD ...
Page 132
... Value on Value on Bit 0 all other POR, BOR Resets RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 0000 0000 0000 RBIP 1111 1111 1111 1111 INT1IF 1100 0000 1100 0000 2004 Microchip Technology Inc. ...
Page 133
... RD PORTC Peripheral Data In Note 1: I/O pins have diode protection Peripheral output enable is only active if peripheral select is active. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. ...
Page 134
... Input/output port pin, addressable USART asynchronous receive or addressable USART synchronous data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 RC1 mode). Value on Value on Bit 0 all other POR, BOR Resets RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
Page 135
... LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 FIGURE 10-9: RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD ...
Page 136
... RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V DS30491C-page 134 Port Data 1 CK Data Latch TRIS Latch and (1) I/O pin TTL Input Buffer 2004 Microchip Technology Inc. ...
Page 137
... IBOV MEMCON EBDIS — WAIT1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function (1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. (1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. ...
Page 138
... EXAMPLE 10-5: CLRF PORTE CLRF LATE MOVLW 03h MOVWF TRISE (Refer to Memory INITIALIZING PORTE ; Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE1:RE0 as inputs ; RE7:RE2 as outputs 2004 Microchip Technology Inc. ...
Page 139
... RD PORTE RD LATE Data Bus WR LATE or PORTE WR TRISE RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 I/O pin TRIS Pin Override RE0 RE1 ...
Page 140
... Bit 2 Bit 1 WAIT0 — — WM1 PSPMODE — — — Value on Value on: Bit 0 all other POR, BOR Resets 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu WM0 0-00 --00 0000 --00 — 0000 ---- 0000 ---- 2004 Microchip Technology Inc. ...
Page 141
... WR LATF or WR PORTF CK Q Data Latch TRISF Q CK TRIS Latch RD TRISF RD PORTF To A/D Converter Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 EXAMPLE 10-6: CLRF PORTF CLRF LATF MOVLW 07h MOVWF CMCON MOVLW 0Fh MOVWF ADCON1 ...
Page 142
... I/O pin WR TRISF Input Buffer D RD PORTF SS Input Note: I/O pins have diode protection to V and RF7 PIN BLOCK DIAGRAM D Q I/O pin CK Data Latch D Q Schmitt Trigger CK Input Buffer TRIS Latch TTL Input Buffer RD TRISF and 2004 Microchip Technology Inc. ...
Page 143
... C2INV CVRCON CVREN CVROE CVRR CVRSS CVR3 Legend unknown unchanged. Shaded cells are not used by PORTF. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output port pin or analog input. Input/output port pin, analog input or comparator 2 output. Input/output port pin, analog input or comparator 1 output. ...
Page 144
... OPMODE2:OPMODE0 = 000 and INITIALIZING PORT ; Initialize PORTG by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs OPMODE2:OPMODE0 = 000 ENDRHI I/O pin Schmitt Trigger 2004 Microchip Technology Inc. ...
Page 145
... WR LATG PORTG Data Latch D Q Schmitt Trigger WR TRISG CK Input Buffer TRIS Latch RD TRISG PORTG CANRX Note: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 TX1SRC OPMODE2:OPMODE0 = 000 and FIGURE 10-19: Data Bus I/O pin WR LATG or WR PORTG ...
Page 146
... RG5/MCLR/V MCLRE Data Bus RD TRISA RD LATA RD PORTA High-Voltage Detect Internal MCLR DS30491C-page 144 P1D Out Auto-Shutdown Q RD TRISG and PIN BLOCK DIAGRAM PP Schmitt Trigger Latch Filter I/O pin Schmitt Trigger Input Buffer RG5/MCLR Low-Level MCLR Detect 2004 Microchip Technology Inc. ...
Page 147
... Legend unknown unchanged Note 1: RG5 is available as an input only when MCLR is disabled. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output port pin or CAN bus transmit output. Input/output port pin, CAN bus complimentary transmit output or CAN bus bit time clock. ...
Page 148
... RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE D Q (1) I/O pin CK Data Latch D Q Schmitt CK Trigger Input TRIS Latch Buffer and RH7:RH4 PINS BLOCK DIAGRAM IN I/O MODE D Q (1) I/O pin CK Data Latch D Q Schmitt Trigger Input CK Buffer TRIS Latch and 2004 Microchip Technology Inc. ...
Page 149
... RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTH RD LATD Data Bus WR LATH or PORTH WR TRISH RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Port Data 1 CK Data Latch ...
Page 150
... Input/output port pin or analog input channel 15. Bit 4 Bit 3 Bit 2 Bit 1 WAIT0 — — WM1 Value on Value on: Bit 0 all other POR, BOR Resets 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 WM0 0-00 --00 0-00 --00 2004 Microchip Technology Inc. ...
Page 151
... Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 FIGURE 10-25: RD LATJ Data Bus D WR LATJ CK or PORTJ Data Latch D WR TRISJ ...
Page 152
... UB/LB Out System Bus Control Drive System Note 1: I/O pins have diode protection to V DS30491C-page 150 Port Data 1 CK Data Latch TRIS Latch and Port Data 1 CK Data Latch TRIS Latch and (1) I/O pin (1) I/O pin 2004 Microchip Technology Inc. ...
Page 153
... LATJ LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ Legend unknown unchanged 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output port pin or address latch enable control for external memory interface. Input/output port pin or output enable control for external memory interface ...
Page 154
... Set Interrupt Flag PSPIF (PIR1<7>) bit PSPMODE Note: I/O pin has protection diodes to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT RDx pin CK Data Latch TTL TRIS Latch Read RD TTL Chip Select CS TTL Write TTL WR and 2004 Microchip Technology Inc. ...
Page 155
... Value at POR FIGURE 10-29: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ...
Page 156
... AD8 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 — 0000 ---- 0000 ---- RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
Page 157
... Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 158
... T0PS2, T0PS1, T0PS0 0 Sync with Internal TMR0L Clocks delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2004 Microchip Technology Inc. ...
Page 159
... T0CS TRISA — PORTA Data Direction Register Legend unknown unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution) ...
Page 160
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 158 2004 Microchip Technology Inc. ...
Page 161
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Figure 12 simplified block diagram of the Timer1 module. Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 162
... CCP Special Event Trigger TMR1 CLR TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize Prescaler det 2 Sleep Input Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Sleep Input 2004 Microchip Technology Inc. ...
Page 163
... RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 12.4 Resetting Timer1 Using a CCP Trigger Output ...
Page 164
... Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared /4) has a prescale option OSC R/W-0 R/W-0 R/W-0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 165
... T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 13.3 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock ...
Page 166
... Timer3. R/W-0 R/W-0 R/W-0 T3CKPS1 T3CKPS0 T3CCP1 /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 T3SYNC TMR3CS TMR3ON bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 167
... Enable Oscillator T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled ...
Page 168
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 0000 0000 0000 CCP2IF -0-0 0000 -0-0 0000 CCP2IE -0-0 0000 -0-0 0000 CCP2IP -1-1 1111 -1-1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2004 Microchip Technology Inc. ...
Page 169
... PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Additionally, the CCP2 special event trigger may be used to start an A/D conversion if the A/D module is enabled. ...
Page 170
... Value at POR DS30491C-page 168 U-0 R/W-0 R/W-0 R/W-0 — DC2B1 DC2B0 CCP2M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCP2M2 CCP2M1 CCP2M0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 171
... PWM Capture None. PWM Compare None. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 An event is selected by control bits CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the inter- rupt request flag bit, CCPxIF (PIR registers), is set. It must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value will be lost ...
Page 172
... Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP1CON with ; this value TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L 2004 Microchip Technology Inc. ...
Page 173
... Q S RC1/CCP2 pin R TRISC<1> Output Enable CCP2CON<3:0> 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 15.3.2 TIMER1/TIMER3 MODE SELECTION The timer used with each CCP module is selected in the T3CCP2:T3CCP1 bits of the T3CON register. Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature ...
Page 174
... CCP1M0 0000 0000 0000 0000 CCP2IF -0-0 0000 -0-0 0000 CCP2IE -0-0 0000 -0-0 0000 CCP2IP -1-1 1111 -1-1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR3ON 0000 0000 uuuu uuuu 2004 Microchip Technology Inc. ...
Page 175
... FIGURE 15-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula. EQUATION 15-1: PWM Period = [(PR2 • ...
Page 176
... CCP1M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M0 --00 0000 --00 0000 2004 Microchip Technology Inc. ...
Page 177
... PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 The control register for CCP1 is shown in Register 16-1. In addition to the expanded functions of the CCP1CON register, the CCP1 module has two ...
Page 178
... RC2 RE6 RE5 CCP1 RE6 RE5 (2) P1A P1B RE5 (2) (2) P1A P1B P1C Set Flag bit CCP1IF Output Logic Match CCP1CON<3:0> Mode Select TMR1H RG4 RG4 RG4 P1D CCPR1H CCPR1L Comparator 0 1 T3CCP2 TMR1L TMR3H TMR3L 2004 Microchip Technology Inc. ...
Page 179
... Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 16.2.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON< ...
Page 180
... CCP1/P1A TRISC<2> P1B TRISE<6> Output R Q Controller P1C TRISE<5> S P1D TRISG<4> CCP1DEL 0 Duty Cycle (1) Delay 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 RC2/CCP1/P1A (2) RE6/AD14/P1B or RH7 (2) RE5/AD13/P1C or RH6 RG4/P1D PR2 + 1 Period (1) Delay 2004 Microchip Technology Inc. ...
Page 181
... Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.2.6 “Programmable Dead-Band Delay”). Relationships: • Period = (PR2 + 1) * (TMR2 prescale value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value) OSC • Delay = (PWM1CON<6:0>) OSC 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 0 Duty Cycle Period (1) Delay Delay PR2 + 1 (1) ...
Page 182
... Dead-band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Period (1) ( FET Driver FET Driver 2004 Microchip Technology Inc. ...
Page 183
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. The TRISC<2>, TRISC<6:5> and TRISG<4> ...
Page 184
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD 2004 Microchip Technology Inc. ...
Page 185
... Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. OFF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D ...
Page 186
... PDC4 PDC3 / cycles between the scheduled time when a PWM signal should OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 187
... PSSBDn: Pins B and D Shutdown State Control bits 00 = Drive pins B and D to ‘0’ Drive pins B and D to ‘1’ Pins B and D tri-state Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 188
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Resumes ECCPASE Cleared by Firmware PWM Resumes 2004 Microchip Technology Inc. ...
Page 189
... ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 ECCP1DEL PRSEN PDC6 PDC5 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 7. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 8. Configure and start TMR2: • ...
Page 190
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 188 2004 Microchip Technology Inc. ...
Page 191
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
Page 192
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 193
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC ...
Page 194
... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. 2004 Microchip Technology Inc. ...
Page 195
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb PROCESSOR 1 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 196
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2004 Microchip Technology Inc. ...
Page 197
... SSPIF Interrupt Flag SSPSR to SSPBUF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. ...
Page 198
... SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS30491C-page 196 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 2004 Microchip Technology Inc. ...
Page 199
... SMP CKE D/A Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 17.3.10 BUS MODE COMPATIBILITY Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
Page 200
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT Reg operation mode operation. The 2 C Slave mode. When the 2004 Microchip Technology Inc. ...