ATTINY28V-1MU Atmel, ATTINY28V-1MU Datasheet - Page 72
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ATTINY28V-1MU
Manufacturer Part Number
ATTINY28V-1MU
Description
IC MCU AVR 2K 1.8V 1.2MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY28V-1MU
Core Processor
AVR
Core Size
8-Bit
Speed
1.2MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Maximum Clock Frequency
1.2 MHz
Number Of Programmable I/os
11
Number Of Timers
1
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Instruction Set Summary (Continued)
72
Mnemonic
DATA TRANSFER INSTRUCTIONS
LD
ST
MOV
LDI
IN
OUT
LPM
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
ATtiny28L/V
Operands
Rd, Z
Z, Rr
Rd, Rr
Rd, K
Rd, P
P, Rr
P, b
P, b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Description
Load Register Indirect
Store Register Indirect
Move between Registers
Load Immediate
In Port
Out Port
Load Program Memory
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left through Carry
Rotate Right through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit Load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half-carry Flag in SREG
Clear Half-carry Flag in SREG
No Operation
Sleep
Watchdog Reset
Operation
Rd ← (Z)
(Z) ← Rr
Rd ← Rr
Rd ← K
Rd ← P
P ← Rr
R0 ← (Z)
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)
Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)
Rd(n) ← Rd(n+1), n = 0..6
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
Flags
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
1062F–AVR–07/06
# Clocks
2
2
1
1
1
1
3
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1