PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 39
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PIC16F72-I/ML
Manufacturer Part Number
PIC16F72-I/ML
Description
IC PIC MCU FLASH 2KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F72-ISO.pdf
(136 pages)
5.PIC16F72-ISO.pdf
(6 pages)
6.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16F72-I/MLR
PIC16F72-I/MLR
PIC16F72-I/MLR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
8.0
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a:
• 16-bit capture register
• 16-bit compare register
• PWM master/slave duty cycle register.
Table 8-1 shows the timer resources of the CCP
Module modes.
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
REGISTER 8-1:
© 2007 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULE
bit 7-6
bit 5-4
bit 3-0
CCPCON1: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
Unimplemented: Read as '0'
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set,
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
bit 7
U-0
—
CCPx pin is unaffected)
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
U-0
—
CCPxX
R/W-0
W = Writable bit
‘1’ = Bit is set
CCPxY
R/W-0
Additional information on the CCP module is available
in the PIC™ Mid-Range MCU Reference Manual,
(DS33023).
TABLE 8-1:
CCP Mode
Compare
CCPxM3
Capture
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PWM
R/W-0
CCP MODE - TIMER
RESOURCE
CCPxM2
R/W-0
PIC16F72
Timer Resource
x = Bit is unknown
CCPxM1
R/W-0
DS39597C-page 37
Timer1
Timer1
Timer2
CCPxM0
R/W-0
bit 0