PIC16LF1939-I/P Microchip Technology, PIC16LF1939-I/P Datasheet - Page 118
![IC MCU 8BIT FLASH 40-DIP](/photos/19/0/190060/4243276_sml.jpg)
PIC16LF1939-I/P
Manufacturer Part Number
PIC16LF1939-I/P
Description
IC MCU 8BIT FLASH 40-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1939-I/P
Core Size
8-Bit
Program Memory Size
28KB (16K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16LF
Eeprom Memory Size
256Byte
Ram Memory Size
1024Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F193X/LF193X
11.3
It is important to understand the Flash program mem-
ory structure for erase and programming operations.
Flash Program memory is arranged in rows. A row con-
sists of a fixed number of 14-bit program memory
words. A row is the minimum block size that can be
erased by user software.
Flash program memory may only be written or erased
if the destination address is in a segment of memory
that is not write-protected, as defined in bits WRT<1:0>
of Configuration Word 2.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the EEDATH:EEDATL register pair.
The number of data write latches is not equivalent to
the number of row locations. During programming, user
software will need to fill the set of write latches and ini-
tiate a programming operation multiple times in order to
fully reprogram an erased row. For example, a device
with a row size of 32 words and eight write latches will
need to load the write latches with data and initiate a
programming operation four times.
The size of a program memory row and the number of
program memory write latches may vary by device.
See Table 11-1 for details.
TABLE 11-1:
DS41364D-page 118
PIC16F193X/
Note:
LF193X
Device
Flash Program Memory Overview
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
EEADRL<4:0> =
FLASH MEMORY
ORGANIZATION BY DEVICE
Erase Block
(Row) Size/
Boundary
32 words,
00000
Number of Write
EEADRL<2:0> =
Boundary
Latches/
8 words,
000
Preliminary
11.3.1
To read a program memory location, the user must:
1.
2.
3.
4.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF EECON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the EEDATH:EEDATL register pair; therefore, it can
be read as two bytes in the following instructions.
EEDATH:EEDATL register pair will hold this value until
another read or until it is written to by the user.
Note 1: The two instructions following a program
Write the Least and Most Significant address
bits to the EEADRH:EEADRL register pair.
Clear the CFGS bit of the EECON1 register.
Set the EEPGD control bit of the EECON1
register.
Then, set control bit RD of the EECON1 register.
2: Flash program memory can be read
READING THE FLASH PROGRAM
MEMORY
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
regardless of the setting of the CP bit.
2009 Microchip Technology Inc.
instruction
on
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