PIC18F26K20-E/SS Microchip Technology, PIC18F26K20-E/SS Datasheet - Page 202
![IC PIC MCU FLASH 32KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F26K20-E/SS
Manufacturer Part Number
PIC18F26K20-E/SS
Description
IC PIC MCU FLASH 32KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-EML.pdf
(430 pages)
Specifications of PIC18F26K20-E/SS
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
64MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K20-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-EML PDF datasheet #5
- Current page: 202 of 456
- Download datasheet (4Mb)
PIC18F2XK20/4XK20
17.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – SCK/SCL
• Serial data (SDA) – SDI/SDA
The user must configure these pins as inputs with the
corresponding TRIS bits.
FIGURE 17-7:
DS41303G-page 202
SDI/SDA
SCK/SCL
I
2
C Mode
Read
Shift
Clock
MSb
MSSP BLOCK DIAGRAM
(I
2
2
SSPMSK Reg
SSPADD Reg
Match Detect
C mode fully implements all
Stop bit Detect
C™ MODE)
SSPBUF Reg
SSPSR Reg
Start and
LSb
Write
(SSPSTAT Reg)
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
17.4.1
The MSSP module has seven registers for I
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
When the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate Generator
reload value. When the SSP is configured for I
mode the SSPADD register holds the slave device
address. The SSP can be configured to respond to a
range of addresses by qualifying selected bits of the
address register with the SSPMSK register.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
(SSPBUF)
accessible
transmission,
REGISTERS
2010 Microchip Technology Inc.
the
2
C mode operation. The
SSPBUF
2
is
C slave
not
2
C
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