AT90PWM216-16SU Atmel, AT90PWM216-16SU Datasheet - Page 124
AT90PWM216-16SU
Manufacturer Part Number
AT90PWM216-16SU
Description
MCU AVR 16K ISP FLSH 16MHZ24SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM216-16SU.pdf
(359 pages)
Specifications of AT90PWM216-16SU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
24-SOIC (7.5mm Width)
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.10 16-bit Timer/Counter Register Description
15.10.1
124
AT90PWM216/316
Timer/Counter1 Control Register A – TCCR1A
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting.
WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 15-2.
Bit
Read/Write
Initial Value
COMnA1/COMnB1
and ICF n
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
0
0
1
1
TCNTn
TCNTn
OCRnx
(clk
as TOP)
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
COM1A1
(if used
Compare Output Mode, non-PWM
R/W
7
0
COM1A0
COMnA0/COMnB0
R/W
6
0
TOP - 1
TOP - 1
Old OCRnx Value
0
1
0
1
COM1B1
R/W
Table 15-2
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OCnA/OCnB disconnected.
Toggle OCnA/OCnB on Compare Match.
Clear OCnA/OCnB on Compare Match (Set output to
low level).
Set OCnA/OCnB on Compare Match (Set output to
high level).
shows the COMnx1:0 bit functionality when the
TOP
TOP
R
3
–
0
BOTTOM
TOP - 1
clk_I/O
R
2
0
–
New OCRnx Value
/8)
WGM11
R/W
1
0
BOTTOM + 1
TOP - 2
WGM10
R/W
0
0
7710E–AVR–08/10
TCCR1A
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