ATMEGA328-MU Atmel, ATMEGA328-MU Datasheet - Page 161
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ATMEGA328-MU
Manufacturer Part Number
ATMEGA328-MU
Description
IC MCU AVR 32K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA328-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA328
Supply Current (max)
0.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8271C–AVR–08/10
Note:
Table 17-7
rect PWM mode.
Table 17-7.
Note:
• Bits 3, 2 – Reserved
These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will
always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
Table 17-8.
Notes:
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Mode
COM2B1
0
1
2
3
4
5
6
7
0
0
1
1
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
1. MAX= 0xFF
2. BOTTOM= 0x00
WGM2
pare Match is ignored, but the set or clear is done at BOTTOM. See
Mode” on page 153
pare Match is ignored, but the set or clear is done at TOP. See
page 153
shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
0
0
0
0
1
1
1
1
Compare Output Mode, Phase Correct PWM Mode
Waveform Generation Mode Bit Description
COM2B0
for more details.
WGM1
0
1
0
1
0
0
1
1
0
0
1
1
for more details.
Description
Normal port operation, OC2B disconnected.
Reserved
Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.
Set OC2B on Compare Match when up-counting. Clear OC2B on
Compare Match when down-counting.
WGM0
Table
0
1
0
1
0
1
0
1
17-8. Modes of operation supported by the Timer/Counter
Timer/Counter
Mode of
Operation
Normal
PWM, Phase
Correct
CTC
Fast PWM
Reserved
PWM, Phase
Correct
Reserved
Fast PWM
”Modes of Operation” on page
OCRA
OCRA
OCRA
0xFF
0xFF
0xFF
TOP
–
–
(1)
”Phase Correct PWM Mode” on
Immediate
Immediate
Update of
BOTTOM
BOTTOM
OCRx at
TOP
TOP
”Phase Correct PWM
–
–
150).
Set on
TOV Flag
BOTTOM
BOTTOM
MAX
MAX
MAX
TOP
–
–
(1)(2)
161
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