PIC18F2221-I/SP Microchip Technology, PIC18F2221-I/SP Datasheet - Page 217
![IC PIC MCU FLASH 2KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2221-I/SP
Manufacturer Part Number
PIC18F2221-I/SP
Description
IC PIC MCU FLASH 2KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18F2221-I/SP
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2221-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2321-IML PDF datasheet #5
- Current page: 217 of 396
- Download datasheet (7Mb)
18.2
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
The
(BAUDCON<5>) bits allow the TX and RX signals to be
inverted (polarity reversed). Devices that buffer signals
between TTL and RS-232 levels also invert the signal.
Setting the TXCKP and RXDTP bits allows for the use of
circuits that provide buffering without inverting the signal.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Break signal
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
• Pin State Polarity
18.2.1
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
© 2007 Microchip Technology Inc.
TXCKP
EUSART Asynchronous Mode
EUSART ASYNCHRONOUS
TRANSMITTER
(BAUDCON<4>)
and
RXDTP
Preliminary
Once the TXREG register transfers the data to the TSR
register (occurs in one T
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
The TXCKP bit (BAUDCON<4>) allows the TX signal to
be inverted (polarity reversed). Devices that buffer sig-
nals from TTL to RS-232 levels also invert the signal
(when TTL = 1, RS-232 = negative). Inverting the polar-
ity of the TX pin data by setting the TXCKP bit allows for
use of circuits that provide buffering without inverting the
signal.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
9.
PIC18F4321 FAMILY
Note 1: The TSR register is not mapped in data
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If the signal from the TX pin is to be inverted, set
the TXCKP bit.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2: Flag bit TXIF is set when enable bit TXEN
memory so it is not available to the user.
is set.
CY
), the TXREG register is empty
DS39689E-page 215
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