PIC16C716-20I/SO Microchip Technology, PIC16C716-20I/SO Datasheet - Page 32

• Manufacturer Part Number: PIC16C716-20I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-20I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PIC16C712/716
4.2.1
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution).
FIGURE 4-2:
TABLE 4-1:
DS41106B-page 30
Address
01h
0Bh,8Bh
81h
85h
Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1:
Note:
RA4/T0CKI
CLKOUT (=Fosc/4)
WDT Enable bit
Watchdog
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
pin
Timer
Reserved bit; Do Not Use.
SWITCHING PRESCALER
ASSIGNMENT
To avoid an unintended device Reset, a
specific instruction sequence (shown in
the PICmicro
Manual, DS33023) must be executed
when changing the prescaler assignment
from Timer0 to the WDT. This sequence
must be followed even if the WDT is
disabled.
Name
TMR0
INTCON
OPTION_REG
TRISA
REGISTERS ASSOCIATED WITH TIMER0
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
®
0
1
Timer0 Module’s Register
RBPU INTEDG T0CS
Bit 7
GIE
PSA
Mid-Range Reference
—
M
U
X
0
1
PEIE
Bit 6
T0CS
—
M
U
X
Bit 5
T0IE
0
—
8-bit Prescaler
8-to-1 MUX
(1)
Time-out
8
M U X
WDT
T0SE
INTE
Bit 4
Bit 4
1
0
1
PSA
PORTA Data Direction Register
M
U
X
RBIE
Bit 3
PSA
4.3
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt
Service Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
Sleep since the timer is shut off during Sleep.
PSA
Bit 2
T0IF
PS2
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
Bit 1
INTF
PS1
RBIF
Bit 0
PS0
© 2005 Microchip Technology Inc.
TMR0 Reg
Data Bus
xxxx xxxx
0000 000x
1111 1111
--11 1111
Value on:
POR,
BOR
8
Set flag bit T0IF
on Overflow
other Resets
Value on all
uuuu uuuu
0000 000u
1111 1111
--11 1111