PIC18LF44J50-I/ML Microchip Technology, PIC18LF44J50-I/ML Datasheet - Page 132
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF44J50-I/ML
Manufacturer Part Number
PIC18LF44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F46J50 FAMILY
9.3
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 9-3:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a POR. The integrated weak pull-ups
consist of a semiconductor structure similar to, but
somewhat different, from a discrete resistor. On an
unloaded I/O pin, the weak pull-ups are intended to
provide logic high indication, but will not necessarily
pull the pin all the way to V
DS39931C-page 132
CLRF
CLRF
MOVLW
MOVFF
MOVLW
MOVWF
Note:
PORTB
LATB
0x3F
WREG ADCON1 ; pins in this example
0CFh
TRISB
PORTB, TRISB and LATB
Registers
On a POR, the RB<3:0> bits are
configured as analog inputs by default and
read as ‘0’; RB<7:4> bits are configured
as digital inputs.
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure as digital I/O
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
DD
levels.
Four of the PORTB pins (RB<7:4>) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep mode or
any of the Idle modes. Application software can clear
the interrupt flag by following these steps:
1.
2.
3.
A mismatch condition continues to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one instruction
cycle of delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB5 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RB5/KBI1/SDI1/SDA1/RP8 pin.
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction).
Wait one instruction cycle (such as executing a
NOP instruction).
Clear flag bit, RBIF.
© 2009 Microchip Technology Inc.
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