PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet - Page 74
![IC PIC MCU FLASH 32K 2V 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F45J50-I/PT
Manufacturer Part Number
PIC18F45J50-I/PT
Description
IC PIC MCU FLASH 32K 2V 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J50-ISS.pdf
(554 pages)
2.PIC18LF24J50-ISS.pdf
(12 pages)
3.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F45J50-I/PT
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Operating Supply Voltage
2.25 V to 2.75 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3776Byte
Cpu Speed
48MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F45J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F46J50 FAMILY
5.1.4.2
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) and the
STKUNF (Stack Underflow) status bits. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
Power-on Reset (POR).
The action that takes place when the stack becomes
full depends on the state of the Stack Overflow Reset
Enable (STVREN) Configuration bit.
Refer to Section 26.1 “Configuration Bits” for device
Configuration bits’ description.
If STVREN is set (default), the 31
(PC + 2) value onto the stack, set the STKFUL bit and
reset the device. The STKFUL bit will remain set and
the Stack Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31
Any additional pushes will not overwrite the 31
and the STKPTR will remain at 31.
REGISTER 5-1:
DS39931C-page 74
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-0
Note 1:
STKFUL
st
R/C-0
push and the Stack Pointer will increment to 31.
(1)
Bits 7 and 6 are cleared by user software or by a POR.
Return Stack Pointer (STKPTR)
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
Unimplemented: Read as ‘0’
SP<4:0>: Stack Pointer Location bits
STKUNF
R/C-0
STKPTR: STACK POINTER REGISTER (ACCESS FFCh)
(1)
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
st
U-0
—
push will push the
(1)
st
R/W-0
push
SP4
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
When the stack has been popped enough times to
unload the stack, the next pop will return zero to the PC
and set the STKUNF bit, while the Stack Pointer
remains at zero. The STKUNF bit will remain set until
cleared by software or until a POR occurs.
5.1.4.3
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execution
is necessary. The PIC18 instruction set includes two
instructions, PUSH and POP, that permit the TOS to be
manipulated under software control. TOSU, TOSH and
TOSL can be modified to place data or a return address
on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
SP3
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
PUSH and POP Instructions
R/W-0
SP2
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
SP1
R/W-0
SP0
bit 0
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