PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7. Module: Master Synchronous Serial Port
8. Module: Master Synchronous Serial Port
FIGURE 1:
 2010 Microchip Technology Inc.
After an I
register may be written for up to 10 T
additional writes are blocked. The data transfer may
be corrupted if SSPxBUF is written during this time.
The WCOL bit is set any time an SSPxBUF write
occurs during a transfer.
Work around
Avoid writing SSPxBUF until the data transfer is
complete, indicated by the setting of the SSP1IF
bit (PIR1<3>).
Verify the WCOL bit (SSPxCON1<7>) is clear after
writing SSPxBUF to ensure any potential transfer
in progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCKx pulse may
occur on the first bit of the transmitted/received
data (see Figure 1).
Work around
To avoid producing the short pulse:
1. Turn off Timer2.
2. Clear the TMR2 register.
3. Load the SSPxBUF with the data to be
4. Turn Timer2 back on.
For sample code, see Example 1.
SDOx
SCKx
transmitted.
Write SSPxBUF
2
(MSSP)
(MSSP)
C transfer is initiated, the SSPxBUF
bit 7 = 1 bit 6 = 0
SCKx PULSE VARIATION
USING TIMER2/2
bit 5 = 1
. . . .
CY
before
PIC18F87J10 FAMILY
EXAMPLE 1:
9. Module: Master Synchronous Serial Port
10. Module: Master Synchronous Serial Port
EXAMPLE 2:
LOOP BTFSS SSP1STAT, BF
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDOx output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data more
than 300 ns after the inactive edge of SCKx.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
When the MSSP peripherals are configured for
SPI mode, the Buffer Full bit, BF (SSPxSTAT<0>)
should not be polled in software to determine when
the transfer is complete.
Work around
Do one of the following:
• Copy the SSPxSTAT register into a variable
• Poll the Master Synchronous Serial Port
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
BRA
MOVF
MOVWF RXDATA
MOVF
BCF
CLRF
MOVWF SSP1BUF
BSF
and perform the bit test on the variable.
(Example 2 copies SSP1STAT into the working
register where the bit test is performed.)
Interrupt Flag bit, SSP1IF (PIR1<3>). This bit
can be polled and will set when the transfer is
complete.
MOVF
BTFSS WREG, BF
BRA
LOOP
SSP1BUF, W
TXDATA, W
T2CON, TMR2ON
TMR2
T2CON, TMR2ON
(MSSP)
(MSSP)
SSP1STAT, W
loop_MSB
AVOIDING THE INITIAL
SHORT SCK1 PULSE
(FOR MSSP1)
Master Synchronous Serial
Port (MSSP1)
;Data received?
;(Xmit complete?)
;No
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on
DS80340B-page 3