PIC16F87-I/SS Microchip Technology, PIC16F87-I/SS Datasheet - Page 134

IC MCU FLASH 4KX14 EEPROM 20SSOP

PIC16F87-I/SS

Manufacturer Part Number
PIC16F87-I/SS
Description
IC MCU FLASH 4KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F87-I/SS

Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F87-I/SS
Manufacturer:
SEMELAB
Quantity:
77
PICmicro MID-RANGE MCU FAMILY
DS31008A-page 8-12
Example 8-2
(such as the PIC16C74A). The user register, W_TEMP, must be defined across all banks and
must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x70
- 0x7F in Bank0). The user register, STATUS_TEMP, must be defined in Bank0.
Within the 70h - 7Fh range (Bank0), wherever W_TEMP is expected the corresponding locations
in the other banks should be dedicated for the possible saving of the W register.
The steps of
1.
2.
3.
4.
5.
If additional locations need to be saved before executing the Interrupt Service Routine (ISR)
code, they should be saved after the STATUS register is saved (step 2), and restored before the
STATUS register is restored (step 4).
Example 8-2: Saving the STATUS and W Registers in RAM
Stores the W register regardless of current bank.
Stores the STATUS register in Bank0.
Executes the Interrupt Service Routine (ISR) code.
Restores the STATUS (and bank select bit register).
Restores the W register.
MOVWF
SWAPF
BCF
MOVWF
:
: (Interrupt Service Routine (ISR) )
:
SWAPF
MOVWF
SWAPF
SWAPF
Example
stores and restores the STATUS and W registers for devices without common RAM
(for Devices without Common RAM)
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
8-2:
; Copy W to a Temporary Register
;
; Swap STATUS nibbles and place
;
; Change to Bank0 regardless of
;
; Save STATUS to a Temporary register
;
; Swap original STATUS register value
;
; Restore STATUS register from
;
; Swap W_Temp nibbles and return
;
; Swap W_Temp to W to restore original
;
regardless of current bank
into W register
current bank
in Bank0
into W (restores original bank)
W register
value to W_Temp
W value without affecting STATUS
1997 Microchip Technology Inc.

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