PIC16F87-I/SS Microchip Technology, PIC16F87-I/SS Datasheet
PIC16F87-I/SS
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PIC16F87-I/SS Summary of contents
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... Microchip Technology Inc. PIC16F87/88 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS30487B ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... SRAM (bytes) Instructions (bytes) PIC16F87 7168 4096 368 PIC16F88 7168 4096 368 2003 Microchip Technology Inc. PIC16F87/88 Pin Diagram 18-Pin DIP, SOIC RA2/AN2/CV RA3/AN3/V RA4/AN4/T0CKI/ RA5/MCLR/V RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1 Note 1: Special Microcontroller Features: • 100,000 erase/write cycles Enhanced FLASH program memory typical • ...
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... PIC16F87/88 Pin Diagrams 18-Pin DIP, SOIC RA2/AN2/CV RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/V RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1 20-Pin SSOP RA2/AN2/CV RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/V RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1 18-Pin DIP & SOIC RA2/AN2/CV RA3/AN3/V REF RA4/AN4/T0CKI/C2OUT RA5/MCLR/V RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1 20-Pin SSOP RA2/AN2/CV RA3/AN3/V ...
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... Pin Diagrams (Cont’d) 28-Pin QFN RA5/MCLR (1) RB0/INT/CCP1 28-Pin QFN RA5/MCLR (1) RB0/INT/CCP1 Note 1: The CCP1 pin is determined by CCPMX in Configuration Word 1 register. 2003 Microchip Technology Inc RA7/OSC1/CLKI 20 2 RA6/OSC2/CLKO PIC16F87 RB7/PGD/T1OSI 15 7 RB6/PGC/T1OSO/T1CKI 21 1 RA7/OSC1/CLKI 2 20 RA6/OSC2/CLKO PIC16F88 RB7/AN6/PGD/T1OSI 7 15 RB6/AN5/PGC/T1OSO/T1CKI Preliminary PIC16F87/88 DS30487B-page 3 ...
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... On-Line Support................................................................................................................................................................................. 209 Systems Information and Upgrade Hot Line ...................................................................................................................................... 209 Reader Response .............................................................................................................................................................................. 210 PIC16F87/88 Product Identification System ...................................................................................................................................... 211 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... The PIC16F87/88 belongs to the Mid-Range family of ® the PICmicro devices. Block diagrams of the devices are shown in Figure 1-1 and Figure 1-2. These devices contain features that are new to the PIC16 product line: • ...
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... PIC16F87/88 FIGURE 1-1: PIC16F87 DEVICE BLOCK DIAGRAM 13 Program Counter FLASH Program Memory 8 Level Stack Program 14 Bus Instruction reg Direct Addr 8 Power-up Instruction Oscillator Start-up Timer Decode & Control Power-on Timing Watchdog Generation OSC1/CLKI Brown-out OSC2/CLKO RA5/MCLR Timer1 Timer2 CCP1 USART Note 1: Higher order bits are from the STATUS register ...
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... RAM Addr 9 Addr MUX Indirect 7 8 Addr FSR reg STATUS reg 3 MUX ALU 8 W reg Timer0 10-bit A/D Data EE Comparators 256 Bytes Preliminary PIC16F87/88 PORTA RA0/AN0 RA1/AN1 RA2/AN2/ REF REF RA3/AN3/V +/C1OUT REF RA4/AN4/T0CKI/C2OUT RA5/MCLR/V PP RA6/OSC2/CLKO RA7/OSC1/CLKI PORTB (2) RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT (2) RB3/PGM/CCP1 ...
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... PIC16F87/88 TABLE 1-2: PIC16F87/88 PINOUT DESCRIPTION PDIP/ SSOP Pin Name SOIC Pin# Pin# RA0/AN0 17 19 RA0 AN0 RA1/AN1 18 20 RA1 AN1 RA2/AN2/ REF REF RA2 AN2 CV REF ( REF RA3/AN3/V +/C1OUT 2 2 REF RA3 AN3 ( REF C1OUT RA4/AN4/T0CKI/C2OUT 3 3 RA4 (4) AN4 T0CKI ...
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... TABLE 1-2: PIC16F87/88 PINOUT DESCRIPTION (CONTINUED) PDIP/ SSOP Pin Name SOIC Pin# Pin# (5) RB0/INT/CCP1 6 7 RB0 INT CCP1 RB1/SDI/SDA 7 8 RB1 SDI SDA RB2/SDO/RX/ RB2 SDO RX DT (5) RB3/PGM/CCP1 9 10 RB3 PGM CCP1 RB4/SCK/SCL 10 11 RB4 SCK SCL RB5/SS/TX/ RB5 RB6/AN5/PGC/T1OSO T1CKI ...
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... PIC16F87/88 NOTES: DS30487B-page 10 Preliminary 2003 Microchip Technology Inc. ...
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... Mid-Range Reference Manual (DS33023). 2.1 Program Memory Organization The PIC16F87/88 devices have a 13-bit program counter capable of addressing program memory space. For the PIC16F87/88, the first (0000h-0FFFh) is physically implemented Figure 2-1). Accessing a location above the physically implemented address will cause a wraparound. For ...
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... PIC16F87/88 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register (FSR). FIGURE 2-2: PIC16F87 REGISTER FILE MAP File Address (*) Indirect addr. Indirect addr. 00h TMR0 01h OPTION 02h PCL 03h STATUS STATUS ...
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... A0h General Purpose Register 80 Bytes EFh F0h accesses 70h-7Fh FFh Bank 2 Bank 1 Preliminary PIC16F87/88 File File Address (*) Indirect addr. 100h 180h 101h OPTION 181h 102h PCL 182h 103h STATUS 183h 104h FSR 184h 105h ...
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... PORTA Data Latch when written; PORTA pins when read (PIC16F87) PORTA Data Latch when written; PORTA pins when read (PIC16F88) 06h PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87) PORTB Data Latch when written; PORTB pins when read (PIC16F88) 07h — ...
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... BRGH ANS5 ANS4 ANS3 ANS2 C2INV C1INV CIS CM2 CVRR — CVR3 CVR2 VCFG1 VCFG0 — — Preliminary PIC16F87/88 Details Value on: Bit 1 Bit 0 on POR, BOR page 26, 135 0000 0000 18, 69 PS1 PS0 1111 1111 135 0000 0000 0001 1xxx ...
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... PIC16F87/88 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 2 (2) 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module Register (2) 102h PCL Program Counter's (PC) Least Significant Byte (2) 103h ...
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... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 R/W-x R/W-x R/W bit 0 (1) (1, Bit is unknown DS30487B-page 17 ...
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... PIC16F87/88 2.2.2.2 OPTION Register The OPTION register is a readable and writable regis- ter that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0, and the weak pull-ups on PORTB. REGISTER 2-2: ...
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... R/W-0 R/W-0 R/W-0 PEIE TMR0IE INTE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 R/W-0 R/W-0 R/W-x TMR0IF INTF RBIF bit Bit is unknown DS30487B-page 19 ...
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... Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TXIE: USART Transmit Interrupt Enable bit ...
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... ADIF: A/D Converter Interrupt Flag bit 1 = The A/D conversion completed (must be cleared in software The A/D conversion is not complete Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) ...
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... PIC16F87/88 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt. REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh) R/W-0 R/W-0 OSFIE CMIE bit 7 bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled ...
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... Value at POR 2003 Microchip Technology Inc. U-0 R/W-0 CMIF — EEIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 U-0 U-0 U-0 U-0 — — — — bit Bit is unknown DS30487B-page 23 ...
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... PIC16F87/88 2.2.2.8 PCON Register Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt ...
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... Implementing a Table Read”. 2.3.2 STACK The PIC16F87/88 family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... PIC16F87/88 2.5 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF reg- ister. Any instruction using the INDF register actually accesses the register pointed to by the File Select Reg- ister, FSR ...
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... When interfacing the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. The PIC16F87/88 devices have 256 bytes of data EEPROM with an address range from 00h to 0FFh. When writing to unimplemented locations, the charge pump will be turned off ...
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... PIC16F87/88 REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch) R/W-x EEPGD bit 7 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-5 Unimplemented: Read as ‘0’ bit 4 FREE: EEPROM Forced Row Erase bit 1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command ...
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... Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. 2003 Microchip Technology Inc. PIC16F87/88 The steps to write to EEPROM data memory are step 10 is not implemented, check the WR bit to see if a write is in progress. ...
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... PIC16F87/88 3.5 Reading FLASH Program Memory To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control (EECON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second instruction cycle to read the data ...
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... Write AAh ; Start Erase (CPU stall) ; Any instructions here are ignored as processor ; halts to begin Erase sequence ; processor will stop here and wait for Erase complete ; after Erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts (if using) Preliminary PIC16F87/88 DS30487B-page 31 ...
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... PIC16F87/88 3.7 Writing to FLASH Program Memory FLASH program memory may only be written to if the destination address segment of memory that is not write protected, as defined in bits WRT1:WRT0 of the device configuration word (Register 15-1). FLASH program memory must be written in four-word blocks. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where EEADR< ...
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... EEDATH ;increment data pointer ;required sequence ;set WR bit to begin write ;instructions here are ignored as processor ;load next word address ;have 4 words been written? ;NO, continue with writing ;YES, 4 words complete, disable writes ;enable interrupts Preliminary PIC16F87/88 DS30487B-page 33 ...
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... PIC16F87/88 3.8 Protection Against Spurious Write There are conditions when the device should not write to the data EEPROM memory. To protect against spu- rious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) EEPROM write. ...
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... OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types The PIC16F87/88 can be operated in eight different oscillator modes. The user can program three configu- ration bits (F 2 select one of these eight OSC OSC modes (modes 5-8 are new PIC16 oscillator configurations Low-Power Crystal 2. XT Crystal/Resonator 3 ...
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... PORTA (RA6). Figure 4-3 shows the pin connections for the ECIO Oscillator mode. To Internal Logic FIGURE 4-3: Clock from Ext. System . OSC2 for DD is 330 Preliminary EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC16F87/88 I/O (OSC2) RA6 2003 Microchip Technology Inc. ...
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... EXT 2003 Microchip Technology Inc. 4.5 Internal Oscillator Block The PIC16F87/88 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This ) val- can eliminate the need for external oscillator circuits on EXT the OSC1 and/or OSC2 pins ...
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... PIC16F87/88 4.5.1 INTRC MODES Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, after which it can be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs F while OSC1 functions as RA7 for digital input and output. • ...
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... WDT, Fail-Safe Clock Monitor, Power-up Timer, and Two-Speed Start-up. The clock sources for the PIC16F87/88 devices are shown in Figure 4-6. See Section 7.0 “Timer1 Mod- ule” for further details of the Timer1 oscillator. See Section 15.1 “ ...
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... PIC16F87/88 4.6.3 CLOCK TRANSITION AND WDT When clock switching is performed, the Watchdog Timer is disabled because the Watchdog ripple counter is used as the Oscillator Start-up Timer. Note: The OST is only used when switching to XT, HS, and LP Oscillator modes. REGISTER 4-2: OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh) ...
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... FIGURE 4-6: PIC16F87/88 CLOCK DIAGRAM Primary Oscillator OSC2 SLEEP OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block 31.25 kHz Source 31.25 kHz (INTRC) 4.6.4 MODIFYING THE IRCF BITS The IRCF bits can be modified at any time, regardless of which clock source is currently being used as the sys- tem clock ...
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... PIC16F87/88 • Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> 000) 1. IRCF bits are modified to a different INTOSC/ INTOSC postscaler frequency. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source ...
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... DLY INP 2003 Microchip Technology Inc. PIC16F87/88 If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed, and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON< ...
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... PIC16F87/88 4.7.2 SEC_RUN MODE The core and peripherals can be configured to be clocked by T1OSC using a 32.768 kHz crystal. The crystal must be connected to the T1OSO and T1OSI pins. This is the same configuration as the low-power timer circuit (see Section 7.6 “Timer1 Oscillator”). When SCS bits are configured to run from T1OSC, a clock transition is generated ...
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... INTRC, the INTRC will be shut down to save current, providing that the INTRC is not being used for any other function, such as WDT, or Fail-Safe Clock monitoring the secondary clock was T1OSC, the T1OSC will continue to run if T1OSCEN is still set, otherwise the T1 oscillator will be shut down. Preliminary PIC16F87/88 DS30487B-page 45 ...
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... PIC16F87/88 FIGURE 4-9: TIMING FOR TRANSITION BETWEEN SEC_RUN/RC_RUN AND PRIMARY CLOCK Sec. Osc OSC1 T OST OSC2 Primary Clock System Clock SCS<1:0> OSTS Program Counter Note 30. typical. INP minimum. OSC SCS INP DLY INP DS30487B-page 46 P (1) INP ( SCS (4) OSC ( (5) T DLY Preliminary ...
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... CPU start-up timers run in parallel. 4. After both the CPU start-up and OST timers have timed out, the device will wait for one addi- tional clock cycle and instruction execution will begin (2) T OSC 0000h 0001h 0003h Preliminary PIC16F87/ 0004h 0005h DS30487B-page 47 ...
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... PIC16F87/88 FIGURE 4-11: PRIMARY SYSTEM CLOCK AFTER RESET (EC, RC, INTRC T1OSI OSC1 OSC2 CPU (2) T CPU Start-up System Clock MCLR OSTS Program PC Counter Note 30. MHz system clock). CPU DS30487B-page 0001h 0002h 0000h Preliminary 0003h 0004h 2003 Microchip Technology Inc. ...
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... INTRC (OST (OST) Preliminary PIC16F87/88 New System Comments Clock INTRC The internal RC oscillator or frequency is dependant INTOSC upon the IRCF bits. or INTOSC Postscaler T1OSC T1OSCEN bit must be enabled LP, XT, HS During the 1024 clocks, program execution is clocked from the second- ary oscillator until the primary oscillator becomes stable ...
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... PIC16F87/88 4.7.4 EXITING SLEEP WITH AN INTERRUPT Any interrupt, such as WDT or INT0, will cause the part to leave the SLEEP mode. The SCS bits are unaffected by a SLEEP command and are the same before and after entering and leaving SLEEP. The clock source used after an exit from SLEEP is determined by the SCS bits ...
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... Input/output, connects to crystal or resonator, oscillator output or 1/4 the frequency of OSC1, and denotes the instruction cycle in RC mode. (1) ST/CMOS Input/output, connects to crystal or resonator or oscillator input. Preliminary PIC16F87/88 pin is a Schmitt Trigger PP inputs. Pins RA<3:0> have TTL REF INITIALIZING PORTA ; select bank of PORTA ; Initialize PORTA by ...
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... ANS6 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: This value applies only to the PIC16F87. 2: This value applies only to the PIC16F88. 3: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. ...
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... REF To A/D Module Channel Input (PIC16F88 only) 2003 Microchip Technology Inc. +/C1OUT PIN REF Comparator Mode = 110 Analog Input Mode Q + Input (PIC16F88 only) REF /V - PIN REF REF Q EN CVROE CV REF Preliminary PIC16F87/ RA3 pin TTL Input Buffer RA2 pin ...
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... PIC16F87/88 FIGURE 5-4: BLOCK DIAGRAM OF RA4/AN4/T0CKI/C2OUT PIN Data Comparator Mode = 011, 101, 110 Bus D Q Comparator 2 Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA TMR0 Clock Input To A/D Module Channel Input (PIC16F88 only) FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/V ...
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... Q RD PORTA Note 1: I/O pins have protection diodes CLKO signal is 1/4 of the F 2003 Microchip Technology Inc. From OSC1 Oscillator Circuit 1x0, 011) OSC V SS Schmitt Trigger Input Buffer 1x0, 011) OSC and frequency. OSC Preliminary PIC16F87/ RA6/OSC2/CLKO pin V SS DS30487B-page 55 ...
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... PIC16F87/88 FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN From OSC2 Data Bus PORTA Q CK Data Latch TRISA CK Q TRIS Latch RD TRISA Q RD PORTA Note 1: I/O pins have protection diodes to V DS30487B-page 56 Oscillator Circuit (F = 011) OSC 10x OSC V SS Schmitt Trigger Input Buffer ...
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... Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. 2003 Microchip Technology Inc. PIC16F87/88 A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for ...
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... PIC16F87/88 TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT/CCP1 bit 0 TTL/ST RB1/SDI/SDA bit 1 TTL/ST RB2/SDO/RX/DT bit 2 TTL/ST (3) RB3/PGM/CCP1 bit 3 TTL/ST RB4/SCK/SCL bit 4 TTL/ST RB5/SS/TX/CK bit 5 TTL RB6/AN5/PGC/T1OSO/ bit 6 TTL/ST T1CKI RB7/AN6/PGD/T1OSI bit 7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt ...
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... Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2003 Microchip Technology Inc. 0 CCP1<M3:M0> = 000 1 Data Latch TRIS Latch TRISB Q RD PORTB and Preliminary PIC16F87/ Weak P Pull-up (1) I/O pin TTL Input Buffer PORTB DS30487B-page 59 ...
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... PIC16F87/88 FIGURE 5-9: BLOCK DIAGRAM OF RB1 PIN 2 I C™ Mode PORT/SSPEN Select SDA Output (2) RBPU Data Latch Data Bus D WR PORTB CK TRIS Latch D WR TRISB CK SDA Drive RD PORTB (3) SDA SDI Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2003 Microchip Technology Inc. SPEN (2) Data Latch TRIS Latch TRISB RD PORTB Schmitt Trigger Buffer and Preliminary PIC16F87/88 SSPEN + SPEN V DD Weak P Pull- (1) I/O pin TTL Input Buffer PORTB DS30487B-page 61 ...
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... PIC16F87/88 FIGURE 5-11: BLOCK DIAGRAM OF RB3 PIN CCP1<M3:M0> = 1000, 1001, 11xx and CCPMX = 0 CCP (2) RBPU Data Latch Data Bus PORTB CK TRIS Latch TRISB CK RD TRISB RD PORTB To PGM or CCP Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SCL Schmitt conforms to the I 2003 Microchip Technology Inc SCL Drive (3) and C™ specification. Preliminary PIC16F87/ Weak P Pull- (1) N I/O pin V SS TTL Input Buffer Latch D EN ...
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... PIC16F87/88 FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN (2) RBPU PORT/SSPEN Data Bus WR PORTB WR TRISB RD TRISB RD PORTB Set RBIF From Other RB7:RB4 pins SS/TX/CK Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2003 Microchip Technology Inc. (2) Data Latch TRIS Latch Analog Input Mode RD TRISB Input Buffer Latch Q RD PORTB Q and Preliminary PIC16F87/ Weak P Pull-up (1) I/O pin TTL PORTB EN Q3 DS30487B-page 65 ...
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... PIC16F87/88 FIGURE 5-15: BLOCK DIAGRAM OF RB7 PIN PORT/Program Mode/ICD PGD Analog Input Mode (2) RBPU Data Latch Data Bus WR PORTB TRIS Latch WR TRISB RD TRISB T1OSCEN PGD DRVEN RD PORTB Set RBIF From Other RB7:RB4 pins PGD To T1OSCI Input To A/D Module Channel Input (PIC16F88 only) ...
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... The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP Sync Cycles T0CS PSA Prescaler 8-bit Prescaler MUX PSA WDT Time-out Preliminary PIC16F87/88 Data Bus 8 TMR0 reg 2 Set Flag bit TMR0IF on Overflow PS2:PS0 PSA DS30487B-page 67 ...
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... PIC16F87/88 6.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x T0CS T0SE PSA PS2 PS1 Preliminary PIC16F87/88 Value on Value on all other POR, BOR RESETS xxxx xxxx uuuu uuuu 0000 000u PS0 1111 1111 1111 1111 DS30487B-page 69 ...
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... PIC16F87/88 NOTES: DS30487B-page 70 Preliminary 2003 Microchip Technology Inc. ...
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... Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. 2003 Microchip Technology Inc. PIC16F87/88 7.1 Timer1 Operation Timer1 can operate in one of three modes: • Timer • Synchronous Counter • ...
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... PIC16F87/88 REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 — T1RUN bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits ...
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... The prescaler, however, will continue to increment. TMR1 TMR1L TMR1ON T1SYNC On/Off 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Preliminary PIC16F87/88 Synchronized 0 Clock Input 1 Synchronize det 2 Q Clock DS30487B-page 73 ...
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... PIC16F87/88 7.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow that will wake-up the processor ...
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... RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L regis- ter pair effectively becomes the period register for Timer1. Preliminary PIC16F87/ OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING ...
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... PIC16F87/88 7.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale ...
Page 79
... INTE RBIE TMR0IF INTF TXIF SSPIF CCP1IF TMR2IF TXIE SSPIE CCP1IE TMR2IE Preliminary PIC16F87/88 Value on Value on Bit 0 all other POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 xxxx xxxx uuuu uuuu ...
Page 80
... PIC16F87/88 NOTES: DS30487B-page 78 Preliminary 2003 Microchip Technology Inc. ...
Page 81
... FIGURE 8-1: Sets Flag TMR2 bit TMR2IF Output RESET Postscaler 1:1 to 1:16 4 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. Preliminary PIC16F87/88 TIMER2 BLOCK DIAGRAM (1) Prescaler TMR2 reg F /4 OSC 1:1, 1:4, 1:16 2 Comparator EQ PR2 reg DS30487B-page 79 ...
Page 82
... PIC16F87/88 REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • ...
Page 83
... Capture Compare PWM R/W-0 R/W-0 R/W-0 CCP1X CCP1Y CCP1M3 CCP1M2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M1 CCP1M0 bit Bit is unknown DS30487B-page 81 ...
Page 84
... PIC16F87/88 9.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on CCP1 pin. An event is defined as: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON< ...
Page 85
... TXIF SSPIF CCP1IF TMR2IF RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Preliminary PIC16F87/88 Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u TMR1IF -000 0000 -000 0000 ...
Page 86
... PIC16F87/88 9.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<x> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
Page 87
... Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE RBIE TMR0IF RCIF TXIF SSPIF CCP1IF RCIE TXIE SSPIE CCP1IE CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Preliminary PIC16F87/88 setting of configuration bit 0x3F 0x1F 0x17 8 7 6.6 Value on Value on Bit 1 Bit 0 all other POR, BOR ...
Page 88
... PIC16F87/88 NOTES: DS30487B-page 86 Preliminary 2003 Microchip Technology Inc. ...
Page 89
... Slave mode (SCK is the clock input) • Clock Polarity (IDLE state of SCK) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) Preliminary PIC16F87/88 register definitions and received simultaneously. To ...
Page 90
... PIC16F87/88 REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 SMP bit 7 bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire SPI Slave mode: This bit must be cleared when SPI is used in Slave mode ...
Page 91
... Value at POR 2003 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) SSPEN CKP SSPM3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 R/W-0 R/W-0 R/W-0 SSPM2 SSPM1 SSPM0 bit Bit is unknown DS30487B-page 89 ...
Page 92
... PIC16F87/88 FIGURE 10-1: SSP BLOCK DIAGRAM (SPI MODE) Read SSPBUF reg RB1/SDI/SDA SSPSR reg bit0 RB2/SDO/RX/DT RB5/SS/ TX/CK SS Control Enable Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RB4/SCK/ SCL TRISB<4> TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION Address Name Bit 7 Bit 6 ...
Page 93
... SCK (CKP = 1) SDO bit 7 bit 6 SDI (SMP = 0) bit 7 SSPIF 2003 Microchip Technology Inc. bit 6 bit 5 bit 3 bit 4 bit 6 bit 5 bit 3 bit 4 bit 2 bit 5 bit 4 bit 3 Preliminary PIC16F87/88 bit 2 bit 1 bit 0 bit 0 bit 0 bit 2 bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 DS30487B-page 91 ...
Page 94
... PIC16F87/88 2 10.3 SSP I C Mode Operation 2 The SSP module mode fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master func- tions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
Page 95
... BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 2003 Microchip Technology Inc. PIC16F87/88 10.3.1.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register ...
Page 96
... PIC16F87/88 TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status bits as Data Transfer is Received SSPSR BF SSPOV Yes Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 2 FIGURE 10- WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R Receiving Address ...
Page 97
... RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 2 C mode) Address Register SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 D R/W Preliminary PIC16F87/ bus Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u -000 0000 -000 0000 ...
Page 98
... PIC16F87/88 NOTES: DS30487B-page 96 Preliminary 2003 Microchip Technology Inc. ...
Page 99
... R/W-0 R/W-0 R/W-0 U-0 TX9 TXEN SYNC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 capability, using 9-bit address R/W-0 R-1 R/W-0 — BRGH TRMT TX9D bit Bit is unknown DS30487B-page 97 ...
Page 100
... PIC16F87/88 REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RB2/SDO/RX/DT and RB5/SS/TX/CK pins as serial port pins Serial port disabled bit 6 RX9: 9-bit Receive Enable bit ...
Page 101
... Microchip Technology Inc. 11.1.1 USART AND INTRC OPERATION The PIC16F87/88 has an 8 MHz INTRC that can be used as the system clock, thereby eliminating the need for external components to provide the clock source. When the INTRC provides the system clock, the USART module will also use the INTRC as its system clock ...
Page 102
... PIC16F87/88 TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = MHz OSC BAUD SPBRG RATE % value (K) KBAUD ERROR KBAUD (decimal) 0.3 — — — 1.2 1.221 +1.75 255 2.4 2.404 +0.17 129 9.6 9.766 +1.73 31 19.2 19.531 + 1.72 15 19.231 28.8 31.250 +8. ...
Page 103
... Preliminary PIC16F87/ MHz OSC SPBRG SPBRG % value value KBAUD ERROR (decimal) (decimal) 103 0.300 1.202 +0. 2.232 -6. — — ...
Page 104
... PIC16F87/88 11.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-to- zero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit baud rate gener- ator can be used to derive standard baud rate frequen- cies from the oscillator ...
Page 105
... SREN CREN — FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TXEN SYNC — BRGH TRMT Preliminary PIC16F87/88 Bit 7/8 STOP Bit STOP Bit START Bit Bit 7/8 Bit 0 Word 2 Word 2 Transmit Shift Reg. Value on Value on: Bit 0 all other POR, BOR RESETS ...
Page 106
... PIC16F87/88 11.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 11-4. The data is received on the RB2/SDO/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate ...
Page 107
... SSPIF CCP1IF TMR2IF TMR1IF SREN CREN — FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE TXEN SYNC — BRGH TRMT Preliminary PIC16F87/88 Value on Value on: Bit 0 all other POR, BOR RESETS R0IF 0000 000x 0000 000u -000 0000 -000 0000 RX9D 0000 -00x 0000 -00x ...
Page 108
... PIC16F87/88 11.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an asynchronous reception with address detect enabled: • Initialize the SPBRG register for the appropriate baud rate high-speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • ...
Page 109
... CCP1IF TMR2IF TMR1IF -000 0000 SREN CREN ADDEN FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 TXEN SYNC — BRGH TRMT Preliminary PIC16F87/88 STOP bit Word 1 RCREG STOP bit Word 1 RCREG Value on Value on: Bit 0 all other POR, BOR RESETS ...
Page 110
... PIC16F87/88 11.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RB5/SS/TX/CK and RB2/SDO/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively ...
Page 111
... SYNC — BRGH TRMT Q3Q4 Q1Q2 Q2Q3 Q4Q1 Q1Q2 bit 1 bit 2 bit 7 bit 0 Word 1 bit 0 bit 2 bit 1 Preliminary PIC16F87/88 Value on Value on: Bit 0 all other POR, BOR RESETS R0IF 0000 000x 0000 000u -000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 ...
Page 112
... PIC16F87/88 11.3.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RB2/SDO/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared ...
Page 113
... SREN CREN ADDEN FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 TXEN SYNC — BRGH TRMT Preliminary PIC16F87/ bit 6 bit 7 ‘0’ Value on Value on: Bit 0 all other POR, BOR RESETS R0IF 0000 000x 0000 000u RX9D 0000 000x 0000 000x ...
Page 114
... PIC16F87/88 11.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a “don't care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP ...
Page 115
... Reference Manual (DS33023). R/W-1 R/W-1 R/W-1 ANS5 ANS4 ANS3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 ® Mid-Range MCU Family R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown DS30487B-page 113 ...
Page 116
... PIC16F87/88 REGISTER 12-2: ADCON0 REGISTER (ADDRESS 1Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 ADCS1 ADCS0 bit 7 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits If ADSC2 = OSC OSC /32 OSC (clock derived from the internal A/D module RC oscillator ADSC2 = OSC /16 OSC /64 OSC (clock derived from the internal A/D module RC oscillator) ...
Page 117
... V - REF REF REF REF REF+ REF- and V external pins to be used. REF - W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 U-0 U-0 U-0 — — — bit Bit is unknown DS30487B-page 115 ...
Page 118
... PIC16F87/88 The ADRESH:ADRESL registers contain the result of the A/D conversion. When the A/D conversion is com- plete, the result is loaded into the A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared, and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 12-1. ...
Page 119
... HOLD delay must complete before acquisition can begin again Sampling Switch leakage V = 0.6V T 500 Preliminary PIC16F87/88 the minimum acquisition time, , see ACQ ® Mid-Range Reference Manual SS C HOLD = DAC capacitance = 51 Sampling Switch (k ) DS30487B-page 117 ...
Page 120
... PIC16F87/88 12.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T A/D conversion requires 9.0 T per 8-bit conversion. AD The source of the A/D conversion clock is software selectable. The seven possible options for T • OSC • OSC • OSC • ...
Page 121
... A/D result will not overwrite these locations (A/D dis- wait, acquisition able), these registers may be used as two general purpose 8-bit registers CYCLES ADRES is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input 10-bit Result 0 7 ADRESH 10-bit Result Preliminary PIC16F87/ ADFM = 0000 00 ADRESL Left Justified DS30487B-page 119 ...
Page 122
... AN6 05h PORTA RA7 RA6 (PIC16F87) (PIC16F88) 05h, 106h PORTB RB7 RB6 (PIC16F87) (PIC16F88) 85h TRISA TRISA7 TRISA6 TRISA5 86h, 186h TRISB TRISB7 TRISB6 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: PIC16F88 only. ...
Page 123
... Figure 13-1. R-0 R/W-0 R/W-0 R/W-0 C1OUT C2INV C1INV - Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 R/W-1 R/W-1 R/W-1 CIS CM2 CM1 CM0 bit Bit is unknown DS30487B-page 121 ...
Page 124
... PIC16F87/88 13.1 Comparator Configuration There are eight modes of operation for the compara- tors. The CMCON register is used to select these modes. Figure 13-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator ...
Page 125
... Pins configured as digital inputs will convert an analog input, according to the Schmitt Trigger input specification. 2: Analog levels, on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Preliminary PIC16F87/88 voltage reference for the + pin of both IN ...
Page 126
... PIC16F87/88 FIGURE 13-3: COMPARATOR OUTPUT BLOCK DIAGRAM To Data Bus Set CMIF bit From other Comparator 13.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred ...
Page 127
... Interconnect Resistance Source Impedance Analog Voltage 2003 Microchip Technology Inc. PIC16F87/88 13.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 13-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V ...
Page 128
... CMIF 8Dh PIE2 OSFIE CMIE 05h PORTA RA7 RA6 (PIC16F87) (PIC16F88) 85h TRISA TRISA7 TRISA6 TRISA5 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. ...
Page 129
... Value Selection 0 VR3:VR0 REF ) RSRC ) + (VR3:VR0/32) (CV ) RSRC RSRC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 ) comes RSRC . It should be noted, however, that the DD – V RSRC SAT and V . RSRC SAT /V - pin. This can be ...
Page 130
... PIC16F87/88 FIGURE 14-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM V DD CVREN 8R RA2/AN2/ pin REF REF CVROE CV REF Input to Comparator TABLE 14-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Address Name Bit 7 Bit 6 9Dh CVRCON CVREN CVROE 9Ch CMCON C2OUT C1OUT Legend unknown unchanged unimplemented, read as ‘0’. ...
Page 131
... With these two timers on-chip, most applications need no external RESET circuitry. 2003 Microchip Technology Inc. PIC16F87/88 SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt ...
Page 132
... PIC16F87/88 REGISTER 15-1: CONFIG1: CONFIGURATION WORD 1 REGISTER (ADDRESS 2007h) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP CCPMX RESV WRT1 WRT0 bit 13 bit 13 CP: FLASH Program Memory Code Protection bits 1 = Code protection off 0 = 0000h to 0FFFh code protected (All protected) bit 12 CCPMX: CCP1 Pin Selection bit ...
Page 133
... Microchip Technology Inc. U-1 U-1 U-1 U-1 U-1 — — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F87/88 U-1 U-1 R/P-1 R/P-1 — — IESO FCMEN bit Bit is unknown DS30487B-page 131 ...
Page 134
... PIC16F87/88 15.2 RESET The PIC16F87/88 differentiates between various kinds of RESET: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during SLEEP • WDT Reset during normal operation • WDT Wake-up during SLEEP • Brown-out Reset (BOR) FIGURE 15-1: ...
Page 135
... For more information, see Application Note, AN607 “Power-up Trouble Shooting” (DS00607). 15.5 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC16F87/ counter that uses the INTRC oscillator as the clock input. This yields a count of 72 ms. While the PWRT is counting, the device is held in RESET. ...
Page 136
... If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes synchronize more than one PIC16F87/88 device operating in parallel. Table 15-3 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 15-4 shows the RESET conditions for all the registers ...
Page 137
... PCL 0000h STATUS 0001 1xxx FSR xxxx xxxx PORTA (PIC16F87) xxxx 0000 PORTA (PIC16F88) xxx0 0000 PORTB (PIC16F87) xxxx xxxx PORTB (PIC16F87) 00xx xxxx PCLATH ---0 0000 INTCON 0000 000x PIR1 -000 0000 PIR2 00-0 ---- TMR1L xxxx xxxx TMR1H xxxx xxxx ...
Page 138
... PIC16F87/88 TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Register Brown-out Reset TXREG 0000 0000 RCREG 0000 0000 ADRESH xxxx xxxx ADCON0 0000 00-0 OPTION 1111 1111 TRISA 1111 1111 TRISB 1111 1111 PIE1 -000 0000 PIE2 00-0 ---- ...
Page 139
... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 15-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK): CASE MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2003 Microchip Technology Inc. PIC16F87/88 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary THROUGH DD ...
Page 140
... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 15.10 Interrupts The PIC16F87/88 has sources of interrupt. The Interrupt Control register (INTCON) records indi- vidual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, ...
Page 141
... OSFIF OSFIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CMIF CMIE 2003 Microchip Technology Inc. PIC16F87/88 TMR0IF TMR0IE INTF INTE RBIF RBIE PEIE GIE Preliminary Wake-up (If in SLEEP mode) Interrupt to CPU DS30487B-page 139 ...
Page 142
... During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- isters during an interrupt (i.e., W, STATUS registers). Since the upper 16 bytes of each bank are common in the PIC16F87/88 devices, temporary holding registers W_TEMP, STATUS_TEMP, should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- text save and restore ...
Page 143
... Watchdog Timer (WDT) For PIC16F87/88 devices, the WDT has been modified from previous PIC16 devices. The new WDT is code and functionally backward compatible with previous PIC16 WDT modules, and allows the user to have a scaler value for the WDT and TMR0 at the same time. ...
Page 144
... PIC16F87/88 TABLE 15-5: PRESCALER/POSTSCALER BIT STATUS Conditions WDTEN = 0 CLRWDT command Oscillator fail detected Exit SLEEP + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit SLEEP + System Clock = XT, HS, LP REGISTER 15-3: WDTCON REGISTER (ADDRESS 105h) U-0 U-0 — — bit 7 bit 7-5 Unimplemented: Read as ‘0’ ...
Page 145
... XT, or HS). 8. System clock is switched to primary source (LP, XT, or HS). The software may read the OSTS bit to determine when the switch over takes place so that any software timing edges can be adjusted 0000h 0001h 0003h Preliminary PIC16F87/88 begin execution by INTRC 0004h 0005h DS30487B-page 143 ...
Page 146
... PIC16F87/88 15.12.4 FAIL-SAFE OPTION The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate even in the event of an oscillator failure. FIGURE 15-10: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral S Q Clock INTRC C ÷ Oscillator 31.25 kHz 488 Hz (32 s) (2.048 ms) The FSCM function is enabled by setting the FCMEN bit in Configuration Word 2 ...
Page 147
... Monitoring the OSTS bit will determine if the crystal is operating. The user should not enter SLEEP mode without handling the fail-safe condition first. 2003 Microchip Technology Inc. PIC16F87/88 2. CONDITIONS: After a POR (Power-on Reset), the device is running in Two-Speed Start-up mode. The crys- tal fails before the OST has expired ...
Page 148
... PIC16F87/88 15.13.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. External RESET input on MCLR pin. 2. Watchdog Timer wake-up (if WDT was enabled). 3. Interrupt from INT pin, RB port change or a peripheral interrupt. External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a “ ...
Page 149
... ID location are used. 2003 Microchip Technology Inc. 15.17 In-Circuit Serial Programming PIC16F87/88 microcontrollers can be serially pro- grammed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage (see Figure 15-13 for an example) ...
Page 150
... RB3 should not be allowed to float if LVP is enabled. An external pull-down device should be used to default the device to normal operating mode. If RB3 floats high, the PIC16F87/88 device will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG register ...
Page 151
... NOP. Note: To maintain upward compatibility with future PIC16F87/88 products, do not use the OPTION and TRIS instructions. All instruction examples use the format ‘0xhh’ to repre- sent a hexadecimal number, where ‘h’ signifies a hexadecimal digit ...
Page 152
... PIC16F87/88 TABLE 16-2: PIC16F87/88 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 153
... Syntax: f,d Operands: Operation: Status Affected: Description: BSF k Syntax: Operands: Operation: Status Affected: Description: Preliminary PIC16F87/88 AND W with f [ label ] ANDWF f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘ ...
Page 154
... PIC16F87/88 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ the next instruction is executed. If bit ‘b’ then the next instruction is discarded and a NOP ...
Page 155
... If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making instruction. CY 2003 Microchip Technology Inc. PIC16F87/88 GOTO Unconditional Branch Syntax: [ label ] Operands Operation: k PC<10:0> ...
Page 156
... PIC16F87/88 IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k Operands 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are OR’d with the eight-bit literal ‘k’. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ label ] IORWF Operands: ...
Page 157
... PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. 2003 Microchip Technology Inc. PIC16F87/88 RLF Rotate Left f through Carry Syntax: [ label ] Operands [0,1] Operation: ...
Page 158
... PIC16F87/88 SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands: ...
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... CAN ® - PowerSmart - Analog 2003 Microchip Technology Inc. PIC16F87/88 17.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
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... PIC16F87/88 17.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
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... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. PIC16F87/88 17.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
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... Demonstration Board The PICDEM 2 Plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the neces- sary hardware and software is included to run the dem- onstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can ...
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... PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 FLASH microcontroller serves as the master. All three micro- controllers are programmed with firmware to provide LIN bus communication. ...
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... PIC16F87/88 NOTES: DS30487B-page 162 Preliminary 2003 Microchip Technology Inc. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2003 Microchip Technology Inc. (except V and MCLR) ................................................... -0. (Note 2) .............................................................................................-0.3 to +14V ) DD > ∑ Preliminary PIC16F87/88 + 0.3V ∑ {( ∑( DS30487B-page 163 ) OL ...
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... PIC16F87/88 FIGURE 18-1: PIC16F87/88 VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V FIGURE 18-2: PIC16LF87/88 VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (12 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10 MHz. ...
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... DC Characteristics: Supply Voltage PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param Symbol Characteristic No. V Supply Voltage DD D001 PIC16LF87/88 D001 PIC16F87/88 D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage POR DD to ensure internal Power-on Reset signal D004 S V Rise Rate ...
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... PIC16F87/88 18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device Typ No. (1) Power-down Current ( PIC16LF87/88 0.1 0.1 0.4 PIC16LF87/88 0 ...
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... DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device Typ No. (2,3) Supply Current ( PIC16LF87/ PIC16LF87/ All devices ...
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... PIC16F87/88 18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device Typ No. (2,3) Supply Current ( All devices 1.8 1 ...
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... DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device Typ No. (2,3) Supply Current ( PIC16LF87/ PIC16LF87/ All devices ...
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... PIC16F87/88 18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device Typ No. (2,3) Supply Current ( PIC16LF87/88 .950 .930 ...
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... DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device Typ No. Module Differential Currents ( I D022 Watchdog Timer 1.5 ...
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... PIC16F87/88 18.3 DC Characteristics: Internal RC Accuracy PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature PIC16F87/88 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature Param Device No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz ...
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... Note oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input not recommended that the PIC16F87/88 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. ...
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... Note oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input not recommended that the PIC16F87/88 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. ...
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... Max V V /24 — V /32 RES — — 1/4 AA — — 1/2 VR — 2k — — — 10 SET Preliminary PIC16F87/88 Units Comments mV – 1.5 V — dB 400 ns PIC16F87/88 600 ns PIC16LF87/ Units Comments LSb LSb Low Range (VRR = 1) LSb High Range (VRR = 0) s DS30487B-page 175 ...
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... PIC16F87/88 18.5 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKO SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
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... All specified values Preliminary PIC16F87/ Units Conditions MHz XT and RC Osc mode MHz HS Osc mode kHz LP Osc mode MHz RC Osc mode MHz XT Osc mode MHz ...
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... DS30487B-page 178 20, 21 Min — — — — — 200 OSC 0 — PIC16F87/88 100 PIC16LF87/88 200 0 PIC16F87/88 — PIC16LF87/88 — PIC16F87/88 — PIC16LF87/88 — OSC Preliminary New Value Typ† Max Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ns (Note 1) ...
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... Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. PIC16F87/ BOR 35 Min Typ† ...
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... PIC16F87/88 30 — — PIC16LF87/88 50 — — 0 — — CY PIC16F87/88 15 — — PIC16LF87/88 25 — — PIC16F87/88 30 — — PIC16LF87/88 50 — — PIC16F87/88 Greater of: — — PIC16LF87/88 Greater of PIC16F87/88 60 — — PIC16LF87/88 100 — — DC — 32.768 2 T — OSC Preliminary 2003 Microchip Technology Inc. ...
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... Microchip Technology Inc Min 0 PIC16F87/88 10 PIC16LF87/ PIC16F87/88 10 PIC16LF87/ PIC16F87/88 — PIC16LF87/88 — PIC16F87/88 — PIC16LF87/88 — Preliminary PIC16F87/88 Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1 ...
Page 184
... PIC16F87/88 FIGURE 18-10: SPI MASTER MODE TIMING (CKE = 0, SMP = SCK (CKP = 0) 71 SCK (CKP = 1) 80 SDO SDI MSb In 73 Note: Refer to Figure 18-3 for load conditions. FIGURE 18-11: SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI ...
Page 185
... SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb In 74 Note: Refer to Figure 18-3 for load conditions. 2003 Microchip Technology Inc Bit MSb 75, 76 Bit LSb Bit 75, 76 Bit LSb In Preliminary PIC16F87/ LSb 77 LSb DS30487B-page 183 ...
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... Condition Note: Refer to Figure 18-3 for load conditions. DS30487B-page 184 Characteristic Min 100 100 PIC16F87/88 — PIC16LF87/88 — — 10 PIC16F87/88 — PIC16LF87/88 — — PIC16F87/88 — PIC16LF87/88 — — 1 Preliminary Typ† Max Units Conditions — — — — — — ...
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... Preliminary PIC16F87/88 Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated 102 92 110 DS30487B-page 185 ...
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... PIC16F87/88 2 TABLE 18-10 BUS DATA REQUIREMENTS Param. Symbol Characteristic No. 100* T Clock high time HIGH 101* T Clock low time LOW 102* T SDA and SCL rise R time 103* T SDA and SCL fall F time 90 START condition SU STA setup time 91 START condition HD STA hold time ...
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... Microchip Technology Inc. 121 Characteristic Min PIC16F87/88 — PIC16LF87/88 — PIC16F87/88 — PIC16LF87/88 — PIC16F87/88 — PIC16LF87/88 — 125 126 Min Typ† 15 — 15 — Preliminary PIC16F87/88 122 Typ† Max Units Conditions — — 100 ns — — — — Max Units Conditions — ...
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... PIC16F87/88 TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16F87/88 (INDUSTRIAL, EXTENDED) Param Sym Characteristic No. A01 N Resolution R A03 E Integral linearity error IL A04 E Differential linearity error DL A06 E Offset error OFF A07 E Gain error GN (3) A10 — Monotonicity A20 V Reference Voltage REF A21 V + Reference voltage high ...
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... T /2 — OSC cycle. CY Preliminary PIC16F87/ NEW_DATA DONE Units Conditions s T based, V 3.0V OSC REF s T based, V 2.0V OSC REF s A/D RC mode s A/D RC mode T AD ...
Page 192
... PIC16F87/88 NOTES: DS30487B-page 190 Preliminary 2003 Microchip Technology Inc. ...
Page 193
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES No Graphs and Tables are available at this time. 2003 Microchip Technology Inc. PIC16F87/88 Preliminary DS30487B-page 191 ...
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... PIC16F87/88 NOTES: DS30487B-page 192 Preliminary 2003 Microchip Technology Inc. ...
Page 195
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2003 Microchip Technology Inc. PIC16F87/88 Example PIC16F87/88-I/P 0310017 Example PIC16F87/88- 04/SO 0310017 Example PIC16F87- 20/SS 0310017 Example PIC16F87 -I/ML 0310017 Preliminary DS30487B-page 193 ...
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... PIC16F87/88 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... L .016 .033 .050 .009 .011 .012 B .014 .017 .020 Preliminary PIC16F87/88 A2 MILLIMETERS MIN NOM MAX 18 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 11.33 11.53 11.73 0.25 0.50 ...
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... PIC16F87/88 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top ...
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... B .009 .011 .014 L .020 .024 .030 R .005 .007 .010 Q .012 .016 .026 CH .009 .017 .024 α 12° Preliminary PIC16F87/ MILLIMETERS* MIN NOM MAX 28 0.65 BSC 0.85 1.00 0.65 0.80 0.00 0.01 0.05 0.20 REF 6.00 BSC 5.75 BSC 3.55 3.70 3 ...
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... PIC16F87/88 NOTES: DS30487B-page 198 Preliminary 2003 Microchip Technology Inc. ...