PIC16F87-I/SS Microchip Technology, PIC16F87-I/SS Datasheet - Page 8

• Manufacturer Part Number: PIC16F87-I/SS
• Description: IC MCU FLASH 4KX14 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F87-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87/88
3.4.2
The RB6 pin is used as a clock input pin, while the RB7
pin is used to enter command bits, and input or output
data during serial operation. To input a command, the
clock pin (RB6) is cycled six times. Each command bit
is latched on the falling edge of the clock, with the Least
Significant bit (LSb) of the command being input first.
The data on RB7 is required to have a minimum setup
(tset1)
specifications), with respect to the falling edge of the
clock. Commands with associated data (read and load)
are specified to have a minimum delay (tdly1) of 1 s
between the command and the data. After this delay,
the clock pin is cycled 16 times, with the first cycle
being a Start bit (0) and the last cycle being a Stop bit
(0). Data is transferred LSb first.
During a read operation, the LSb will be transmitted
onto RB7 on the rising edge of the second cycle, while,
during a load operation, the LSb will be latched on the
falling edge of the second cycle. A minimum 1 s delay
(tdly2) is specified between consecutive commands.
All commands and data words are transmitted LSb first.
The data is transmitted on the rising edge and latched
on the falling edge of the clock. To allow decoding of
commands and reversal of data pin configuration, a
time separation of at least 1 s (tdly1) is required
between a command and a data word, or another
command.
The available commands are described in the following
paragraphs and listed in Table 3-1.
3.4.2.1
Upon receipt of the Load Configuration command, the
PC will be set to 0x2000 and the data sent with the
command is discarded. The four ID locations and the
Configuration Words can then be programmed using
the normal programming sequence, as described in
Section 3.4 “Program Mode”. A description of the
memory mapping schemes of the program memory for
normal operation and Configuration mode operation is
shown in Figure 3-1. Once the configuration memory is
entered, the only way to get back to the user program
memory is to exit the Program/Verify Test mode by
taking MCLR low (V
3.4.2.2
After receiving this command, the chip will load one
word (with 14 bits as a “data word”) to be programmed
into user program memory when 16 cycles are applied.
A timing diagram for this command is shown in
Figure 7-1.
DS39607C-page 8
and
SERIAL PROGRAM OPERATION
Load Configuration
Load Data for Program Memory
hold
IL
).
(thold1)
time
(see
AC/DC
3.4.2.3
After receiving this command, the chip will load a 14-bit
“data word” when 16 cycles are applied. However, the
data memory is only 8 bits wide and, thus, only the first
8 bits of data after the Start bit will be programmed into
the data memory (8 data bits and 6 zeros). It is still
necessary to cycle the clock the full 16 cycles in order
to allow the internal circuitry to reset properly. The data
memory contains up to 256 bytes. If the device is code
protected, the data is read as all zeros. A timing
diagram for this command is shown in Figure 7-2.
3.4.2.4
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The RB7 pin will
go into Output mode on the second rising clock edge,
reverting to Input mode (high-impedance) after the 16th
rising edge. A timing diagram of this command is
shown in Figure 7-3.
3.4.2.5
After receiving this command, the chip will transmit
data bits out of the data memory, starting with the
second rising edge of the clock input. The RB7 pin will
go into Output mode on the second rising edge,
reverting to Input mode (high-impedance) after the 16th
rising edge. As previously stated, the data memory is
8-bits wide and, therefore, only the first 8 bits that are
output are actual data. A timing diagram for this
command is shown in Figure 7-4.
3.4.2.6
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 7-5.
Note:
Upon entering Programming mode, a
“Load Data for Program Memory” or “Load
Data for Data Memory” command of 0x01
must be given before a Begin Erase or
Begin Programming command is initiated.
This will ensure that the programming
pointer is pointing to the correct location in
data or program memory.
Load Data for Data Memory
Read Data from Program Memory
Read Data from Data Memory
Increment Address
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