DSPIC33FJ12GP202-I/ML Microchip Technology, DSPIC33FJ12GP202-I/ML Datasheet - Page 34

• Manufacturer Part Number: DSPIC33FJ12GP202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33F
9.0
9.1
The dsPIC33F instruction set provides a broad suite of
instructions which supports traditional microcontroller
applications, and a class of instructions which supports
math-intensive applications. Since almost all of the
functionality of the PICmicro
been maintained, this hybrid instruction set allows a
friendly DSP migration path for users already familiar
with the PICmicro microcontroller.
9.2
The dsPIC33F instruction set contains 84 instructions
which can be grouped into the ten functional categories
shown in Table 9-1. Table 9-2 defines the symbols
used in the instruction summary tables, Table 9-3
through Table 9-12. These tables define the syntax,
description, storage and execution requirements
for each instruction. Storage requirements are repre-
sented in 24-bit instruction words and execution
requirements are represented in instruction cycles.
Most instructions have several different addressing
modes and execution flows which require different
instruction variants. For instance, there are six unique
ADD instructions and each instruction variant has its
own instruction encoding.
TABLE 9-1:
DS70155C-page 32
Move Instructions
Math Instructions
Logic Instructions
Rotate/Shift Instructions
Bit Instructions
Compare/Skip Instructions
Program Flow Instructions
Shadow/Stack Instructions
Control Instructions
DSP Instructions
Functional Group
dsPIC33F INSTRUCTION SET
Introduction
Instruction Set Overview
dsPIC33F INSTRUCTION
GROUPS
®
MCU instruction set has
Summary Table
Table 9-10
Table 9-12
Table 9-11
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
Table 9-9
Preliminary
9.2.1
As the instruction summary tables show, most
instructions execute in a single cycle with the following
exceptions:
• Instructions DO, MOV.D, POP.D, PUSH.D,
• Instructions DIVF, DIV.S, DIV.U are single-
• Instructions that change the program counter also
• The RETFIE, RETLW and RETURN are special
9.2.2
As the instruction summary tables show, almost all
instructions consume one instruction word (24 bits),
with the exception of the CALL, DO and GOTO
instructions, which are flow instructions listed in
Table 9-9. These instructions require two words of
memory because their opcodes embed large literal
operands.
TBLRDH, TBLRDL, TBLWTH and TBLWTL
require 2 cycles to execute.
cycle instructions, which should be executed
18 consecutive times as the target REPEAT
instruction.
require 2 cycles to execute, with the extra cycle
executed as a NOP. Skip instructions, which skip
over a 2-word instruction, require 3 instruction
cycles to execute with 2 cycles executed as a
NOP.
cases of instructions that change the program
counter. These execute in 3 cycles unless an
exception is pending, and then they execute in
2 cycles.
Note:
MULTI-CYCLE INSTRUCTIONS
MULTI-WORD INSTRUCTIONS
Instructions that access program memory
as data, using Program Space Visibility,
incur some cycle count overhead.
© 2005 Microchip Technology Inc.