PIC16F872-I/SS Microchip Technology, PIC16F872-I/SS Datasheet - Page 68

• Manufacturer Part Number: PIC16F872-I/SS
• Description: IC MCU FLASH 2KX14 EE 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-I/SS

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPAC164020 - MODULE SKT PROMATEII 44TQFPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / Rohs Status: Details

PIC16F872
9.2.10
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I
module is in the IDLE state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (T
times out if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high for one T
then followed by assertion of the SDA pin (SDA is low)
for one T
RSEN bit in the SSPCON2 register will be automati-
cally cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the baud rate generator has timed out.
FIGURE 9-13:
DS30221C-page 66
Note 1: If RSEN is programmed while any other
2: A bus collision during the Repeated
BRG
I
START CONDITION TIMING
event is in progress, it will not take effect.
2
START condition occurs if:
• SCL goes low before SDA is
• SDA is sampled low when SCL
C MASTER MODE REPEATED
, while SCL is high. Following this, the
goes from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Falling edge of ninth clock
BRG
). When the baud rate generator
REPEAT START CONDITION WAVEFORM
SDA
SCL
End of Xmit
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change).
BRG
. This action is
2
C
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
9.2.10.1
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Sr = Repeated START
T
BRG
At completion of START bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
and set SSPIF
Write to SSPBUF occurs here
T
WCOL Status Flag
BRG
1st Bit
T
BRG
© 2006 Microchip Technology Inc.