DSPIC30F2010-20I/SO Microchip Technology, DSPIC30F2010-20I/SO Datasheet - Page 115

• Manufacturer Part Number: DSPIC30F2010-20I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/SOG; DSPIC30F201020IS

18.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least one clock
cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module or external interrupts.
18.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling
sequencing. The ADCBUF will not be updated with the
partially completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an auto
start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multichannel group conversion sequence.
© 2008 Microchip Technology Inc.
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the A/D at the maximum
specified conversion speed, the Auto
Convert Trigger option should be selected
(SSRC = 111) and the Auto Sample Time
bits
(SAMC = 00001). This configuration will
give a total conversion period (sample +
convert) of 13 T
The use of any other conversion trigger
will result in additional T
synchronize the external event to the A/D.
should
AD
be
.
(Auto-Start mode), the
set
AD
to
cycles to
AD
1
wait is
T
AD
18.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
EQUATION 18-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
"Electrical Characteristics" for minimum T
other operating conditions.
Example 18-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 18-1:
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 5
Selecting the A/D Conversion
Clock
T
ADCS<5:0> = 2
Actual T
AD
= T
ADCS<5:0> = 2
CY
dsPIC30F2010
AD
T
T
* (0.5 * (ADCS<5:0> + 1))
AD
CY
DD
= 2 •
= 4.09
=
=
= 99 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 84 nsec
= 33 nsec (30 MIPS)
= 5V). Refer to Section 22.0
T
33 nsec
T
T
CY
2
AD
CY
84 nsec
2
33 nsec
(ADCS<5:0> + 1)
T
T
– 1
AD
CY
AD
(5 + 1)
DS70118H-page 115
. The source of the
– 1
– 1
AD
AD
.
AD
under
time