DSPIC30F2012-30I/SP Microchip Technology, DSPIC30F2012-30I/SP Datasheet - Page 7

• Manufacturer Part Number: DSPIC30F2012-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2012-30I/SP

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F201230ISP

6. Module: Output Compare
7. Module: Output Compare
© 2010 Microchip Technology Inc.
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The Output Compare module is configured
When these events occur, the Output Compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
Affected Silicon Revisions
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
The second problem is that on the next cycle after
the glitch, the OC pin does not go high, or in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
Affected Silicon Revisions
A1
A1
high using the Output Compare module or a
write to the associated PORT register.
and enabled to drive the pin low at some
point in later time (OCxCON = 0x0002 or
OCxCON = 0x0003).
X
X
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
Output Compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
CY
) after the module is enabled.
CY
.
8. Module: ADC
9. Module: PLL
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero. This means that if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
If 4x or 8x PLL mode is used, the input frequency
range is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
Work around
None. If 4x or 8x PLL is used, make sure the input
crystal or clock frequency is 5 MHz or greater.
Affected Silicon Revisions
A1
A1
X
X
dsPIC30F2011/2012
DS80450D-page 7