PIC24HJ32GP204-I/PT Microchip Technology, PIC24HJ32GP204-I/PT Datasheet - Page 107

• Manufacturer Part Number: PIC24HJ32GP204-I/PT
• Description: IC PIC MCU FLASH 32K 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP204-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-2:
10.6.3
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24H devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.6.3.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
© 2011 Microchip Technology Inc.
Note:
Write 0x46 to OSCCON<7:0>.
Write 0x57 to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
SCK1OUT
Function
SS1OUT
U1RTS
SDO1
NULL
U1TX
PIC24HJ32GP202/204 AND PIC24HJ16GP304
OC1
OC2
CONTROLLING CONFIGURATION
CHANGES
MPLAB
language functions for unlocking the
OSCCON register:
See MPLAB Help for more information.
Control Register Lock
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
®
C30
provides
RPnR<4:0>
00000
00011
00100
00111
01000
01001
10010
10011
built-in
C
RPn tied to default port pin
RPn tied to UART1 Transmit
RPn tied to UART1 Ready To Send
RPn tied to SPI1 Data Output
RPn tied to SPI1 Clock Output
RPn tied to SPI1 Slave Select Output
RPn tied to Output Compare 1
RPn tied to Output Compare 2
10.6.3.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
10.6.3.3
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY con-
figuration bit (FOSC<5>) blocks the IOLOCK bit from
being cleared after it has been set once.
In the default (unprogrammed) state, IOL1WAY is set
restricting the users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
10.7
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices implement 17 registers for remappable
peripheral configuration:
• Input Remappable Peripheral Registers (9)
• Output Remappable Peripheral Registers (8)
Note:
Peripheral Pin Select Registers
Input and Output Register values can only
be changed if the IOLOCK bit (OSC-
CON<6>) = 0. See
“Control Register Lock”
command sequence.
Continuous State Monitoring
Configuration Bit Pin Select Lock
Output Name
DS70289G-page 107
Section 10.6.3.1
for a specific