DSPIC33FJ16MC304-I/ML Microchip Technology, DSPIC33FJ16MC304-I/ML Datasheet - Page 40

IC DSPIC MCU/DSP 16K 44QFN

DSPIC33FJ16MC304-I/ML

Manufacturer Part Number
DSPIC33FJ16MC304-I/ML
Description
IC DSPIC MCU/DSP 16K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-I/ML

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
35
Flash Memory Size
16KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16MC304-I/ML
Manufacturer:
Microchip
Quantity:
235
4.1.1
The
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
4.1.2
All
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
FIGURE 4-2:
DS70291D-page 40
program
0x000001
0x000003
0x000005
0x000007
Address
msw
PROGRAM MEMORY
ORGANIZATION
INTERRUPT AND TRAP VECTORS
memory
Program Memory
PROGRAM MEMORY ORGANIZATION
‘Phantom’ Byte
(read as ‘0’)
00000000
00000000
00000000
00000000
space
dsPIC33FJ32MC302/304,
most significant word
devices
is
23
organized
reserve
and
Preliminary
the
in
16
Instruction Width
addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user application at 0x000000, with the actual
address for the start of code at 0x000002.
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the device interrupt sources to be
handled by separate Interrupt Service Routines (ISRs).
A more detailed discussion of the interrupt vector
tables is provided in Section 7.1 “Interrupt Vector
Table”.
least significant word
8
© 2009 Microchip Technology Inc.
0
dsPIC33FJ64MCX02/X04
(lsw Address)
PC Address
0x000000
0x000002
0x000004
0x000006

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