PIC18F6390-I/PT Microchip Technology, PIC18F6390-I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC18F6390-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6390-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6390/6490/8390/8490
TABLE 5-2:
DS39629B-page 78
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.
EUSART1 Baud Rate Generator
EUSART1 Receive Register
EUSART1 Transmit Register
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
Data Direction Control Register for PORTF
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
TRISA7
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
RA7
CSRC
SPEN
Bit 7
—
—
—
—
—
—
—
—
—
PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
(5)
(5)
(5)
TRISA6
PLLEN
LATA6
LCDIP
LCDIF
LCDIE
RA6
CMIP
CMIE
CMIF
ADIP
ADIE
Bit 6
ADIF
RX9
TX9
—
—
—
(5)
(5)
(3)
(5)
Data Direction Control Register for PORTA
Read PORTA Data Latch, Write PORTA Data Latch
Read PORTA pins, Write PORTA Data Latch
RC2IP
RC2IF
RC2IE
RC1IP
RC1IF
RC1IE
RG5
SREN
TXEN
Bit 5
—
—
—
—
—
—
(4)
Data Direction Control Register for PORTG
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTG pins <4:0>, Write PORTG Data Latch <4:0>
SYNC
CREN
TX2IP
TX2IE
TX2IF
TX1IP
TX1IF
TX1IE
TUN4
Bit 4
—
—
—
Preliminary
SENDB
ADDEN
BCLIP
BCLIE
SSPIP
SSPIF
SSPIE
BCLIF
TUN3
Bit 3
—
—
—
—
—
—
CCP1IP
CCP1IE
HLVDIP
HLVDIF
HLVDIE
CCP1IF
BRGH
FERR
TUN2
Bit 2
—
—
—
—
—
—
TMR3IP
TMR3IE
TMR2IP
TMR2IE
TMR3IF
TMR2IF
OERR
TRMT
TUN1
Bit 1
—
—
—
—
—
—
 2004 Microchip Technology Inc.
CCP2IP
CCP2IE
TMR1IP
TMR1IF
TMR1IE
CCP2IF
TX9D
RX9D
TUN0
Bit 0
—
—
—
—
—
—
0000 0000
0000 0000
0000 0000
0000 0000
0000 000x
-111 ----
-000 ----
-000 ----
11-- 1111
00-- 0000
00-- 0000
-111 1111
-000 0000
-000 0000
00-0 0000
1111 1111
1111 1111
---1 1111
1111 1111
1111 ----
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
POR, BOR
Value on
on page:
61, 201
61, 208
61, 206
61, 198
61, 199
61, 106
61, 100
61, 103
61, 105
61, 102
61, 104
61, 101
62, 130
62, 128
62, 126
62, 124
62, 121
62, 130
62, 128
62, 126
62, 124
62, 121
62, 130
62, 128
62, 126
62, 124
62, 121
Details
62, 119
62, 117
62, 114
62, 111
62, 119
62, 117
62, 114
62, 111
62, 119
62, 117
62, 114
62, 111
61, 99
61, 98
35, 61