ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 36

• Manufacturer Part Number: ATMEGA328P-AU
• Description: MCU AVR 32K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA328P-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA328P-20AU; ATMEGA328P-20AU; Q3790246

9.9
9.10
9.11
8271D–AVR–05/11
Clock Output Buffer
Timer/Counter Oscillator
System Clock Prescaler
Table 9-16.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
36
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
ATmega48A/PA/88A/PA/168A/PA/328/P uses the same crystal oscillator for Low-frequency
Oscillator and Timer/Counter Oscillator. See
details on the oscillator and crystal requirements.
ATmega48A/PA/88A/PA/168A/PA/328/P share the Timer/Counter Oscillator Pins (TOSC1 and
TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock
needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Coun-
ter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system
clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See
description on selecting external clock as input instead of a 32.768kHz watch crystal.
The ATmega48A/PA/88A/PA/168A/PA/328/P has a system clock prescaler, and the system
clock can be divided by setting the
ture can be used to decrease the system clock frequency and the power consumption when the
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
and clk
BOD enabled
Fast rising power
Slowly rising power
for details.
Power Conditions
FLASH
are divided by a factor as shown in
Start-up Times for the External Clock Selection
ATmega48A/PA/88A/PA/168A/PA/328/P
”Asynchronous Operation of Timer/Counter2” on page 157
Start-up Time from Power-
down and Power-save
”CLKPR – Clock Prescale Register” on page
Reserved
6 CK
6 CK
6 CK
”Low Frequency Crystal Oscillator” on page 33
Table 29-12 on page
Additional Delay from
”System Clock Prescaler” on page
Reset (V
14CK + 4.1ms
14CK + 65ms
14CK
324.
CC
= 5.0V)
I/O
, clk
387. This fea-
ADC
for further
SUT1...0
, clk
01
00
10
11
CPU
for
36
,