PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 11

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PIC18F86J50-I/PT

Manufacturer Part Number
PIC18F86J50-I/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F86J50-I/PT

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
65
Ram Memory Size
3904Byte
Cpu Speed
48MHz
No. Of Timers
5
No. Of
RoHS Compliant
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
I2C, MSSP, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
65
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F86J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
3.2
Programming code memory is accomplished by first
loading data into the write buffer and then initiating a
programming sequence. The write buffer for all
PIC18F6XJXX/8XJXX devices is 64 bytes. It can be
mapped to any location of the same size beginning at
000000h. The actual memory write sequence takes the
contents of this buffer and programs the proper amount
of code memory that contains the Table Pointer.
Write buffer locations are not cleared following a write
operation. The buffer retains its data after the write is
complete. This means that the buffer must be written
with 64 bytes on each operation. If there are locations
in the code memory that are to remain empty, the
corresponding locations in the buffer must be filled with
FFFFh. This avoids rewriting old data from the previous
cycle.
TABLE 3-2:
© 2006 Microchip Technology Inc.
Step 1: Enable writes.
Step 2: Load write buffer.
Step 3: Repeat for all but the last two bytes. Any unused locations should be filled with FFFFh.
Step 4: Load write buffer for last two bytes.
To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop.
Command
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
4-Bit
Code Memory Programming
84 A6
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
WRITE CODE MEMORY CODE SEQUENCE
Data Payload
BSF
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
EECON1, WREN
PIC18F6XJXX/8XJXX
The programming duration is externally timed and is
controlled by PGC. After a Start Programming
command is issued (4-bit command, ‘1111’), a NOP is
issued, where the 4th PGC is held high for the duration
of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The
PIC18F6XJXX/8XJXX device is shown in Table 3-2.
The flowchart shown in Figure 3-3 depicts the logic
necessary to completely write a PIC18F6XJXX/8XJXX
device. The timing diagram that details the Start
Programming command and parameters P9 and P10 is
shown in Figure 3-4.
Note:
Core Instruction
code
The TBLPTR register must point to the
same region when initiating the program-
ming sequence as it did when the write
buffers were loaded.
sequence
to
DS39644E-page 11
program
a

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