PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 16

• Manufacturer Part Number: PIC18F86J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 65
• Ram Memory Size: 3904Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F6XJXX/8XJXX
5.0
The Configuration Words of the PIC18F6XJXX/8XJXX
devices are implemented as volatile memory registers, as
opposed to the programmable nonvolatile memory used
in other PIC18 devices. All of the Configuration registers
(CONFIG1L, CONFIG1H, CONFIG2L, CONFIG2H,
CONFIG3L and CONFIG3H) are automatically loaded
following each device Reset.
The data for these registers is taken from the four Flash
Configuration Words located at the top of program
memory. Configuration data is stored in order, starting
with CONFIG1L in the lowest Flash address and
ending with CONFIG4H in the highest. The mapping to
specific Configuration Words is shown in Table 5-1.
While four words are reserved in program memory,
only three words (CONFIG1L through CONFIG3H) are
used for device configuration. Users should always
reserve these locations for Configuration Word data
and write their application code accordingly.
The upper four bits of each Configuration Word should
always be stored in program memory as ‘1111’. This is
done so these program memory addresses will always
be ‘1111 xxxx xxxx xxxx’ and interpreted as a NOP
instruction if they were ever to be executed. Because
the corresponding bits in the Configuration Word are
unimplemented, they will not be written to.
TABLE 5-2:
DS39644E-page 16
300000h CONFIG1L DEBUG
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L
300005h CONFIG3H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
File Name
2:
3:
4:
5:
CONFIGURATION WORD
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it
is accidentally executed.
This bit should always be maintained ‘0’.
Implemented in 80-pin devices only.
DEVID registers are read-only and cannot be programmed by the user.
Implemented in PIC18FXXJ10/8XJ15 devices only
(4)
(4)
CONFIGURATION BITS AND DEVICE IDs
WAIT
DEV10
DEV2
IESO
Bit 7
—
—
—
(1)
(1)
(1)
(3)
FCMEN
XINST
BW
DEV1
DEV9
Bit 6
—
—
—
(1)
(1)
(1)
(3)
STVREN
EMB1
DEV0
DEV8
Bit 5
—
—
—
—
(1)
(1)
(1)
(3)
EMB0
REV4
DEV7
Bit 4
—
—
—
—
—
(1)
(1)
(1)
(3)
EASHFT
WDTPS3
REV3
DEV6
Bit 3
—
—
—
—
The Configuration and Device ID registers are
summarized in Table 5-2. A listing of the individual
Configuration bits and their options is provided in
Table 5-3.
TABLE 5-1:
(2)
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
CONFIG4L
CONFIG4H
Note 1:
Configuration
(3)
WDTPS2
Byte
2:
FOSC2
REV2
DEV5
Bit 2
CP0
—
—
—
See Table 2-2 for the complete addresses
within code space for specific devices and
memory sizes.
Unimplemented in PIC18F6XJXX/8XJXX
devices.
(2)
(2)
ECCPMX
WDTPS1
MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
REGISTERS
FOSC1
REV1
DEV4
Bit 1
Code Space
—
—
—
Address
XXXFBh
XXXFCh
XXXFDh
XXXFEh
XXXF8h
XXXF9h
XXXFAh
XXXFFh
© 2006 Microchip Technology Inc.
(3, 5)
WDTPS0
CCP2MX
WDTEN
FOSC0
(1)
REV0
DEV3
Bit 0
—
—
Configuration
Unprogrammed
See Table 5-4
See Table 5-4
Register
Address
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
111- ---1
---- 01--
11-- -111
---- 1111
1111 1---
---- --11
Default/
Value