PIC16LF871-I/P Microchip Technology, PIC16LF871-I/P Datasheet - Page 70
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PIC16LF871-I/P
Manufacturer Part Number
PIC16LF871-I/P
Description
IC PIC MCU FLASH 2KX14 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF871-I/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Oscillator Type
External
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16LF
No. Of I/o's
33
Eeprom Memory Size
64Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
No.
RoHS Compliant
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
PSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
28 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF871-I/PT
Manufacturer:
TI
Quantity:
212
Company:
Part Number:
PIC16LF871-I/PT
Manufacturer:
MICROCHIP
Quantity:
3 000
Company:
Part Number:
PIC16LF871-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16LF871-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F870/871
9.2.2
The receiver block diagram is shown in Figure 9-4. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter, operating at x16 times the baud
rate; whereas, the main receive serial shifter operates
at the bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
register (RSR). After sampling the STOP bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
FIGURE 9-4:
FIGURE 9-5:
DS30569B-page 68
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
F
USART ASYNCHRONOUS
RECEIVER
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RC7/RX/DT
OSC
OSC
Baud Rate Generator
START
x64 Baud Rate CLK
USART RECEIVE BLOCK DIAGRAM
ASYNCHRONOUS RECEPTION
bit
.
SPBRG
Pin Buffer
and Control
bit0
SPEN
bit1
bit7/8
Data
Recovery
Interrupt
STOP
or
64
16
bit
CREN
Word 1
RCREG
START
bit
bit0
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
RCIF
RCIE
RX9
MSb
STOP
RX9D
(8) 7
bit7/8 STOP
Word 2
RCREG
OERR
RCREG Register
RSR Register
bit
START
8
Data Bus
2003 Microchip Technology Inc.
bit
1
FERR
0
START
bit7/8
FIFO
LSb
STOP
bit