PIC16LF871-I/P Microchip Technology, PIC16LF871-I/P Datasheet - Page 79
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PIC16LF871-I/P
Manufacturer Part Number
PIC16LF871-I/P
Description
IC PIC MCU FLASH 2KX14 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF871-I/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Oscillator Type
External
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16LF
No. Of I/o's
33
Eeprom Memory Size
64Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
No.
RoHS Compliant
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
PSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
28 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF871-I/PT
Manufacturer:
TI
Quantity:
212
Company:
Part Number:
PIC16LF871-I/PT
Manufacturer:
MICROCHIP
Quantity:
3 000
Company:
Part Number:
PIC16LF871-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16LF871-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
9.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 9-11:
2003 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.
USART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
(1)
(1)
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
SREN
TXEN
RCIF
RCIE
Bit 5
T0IE
CREN ADDEN
SYNC
INTE
TXIE
Bit 4
TXIF
RBIE
Bit 3
—
—
—
When setting up a Synchronous Slave Reception,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
BRGH
FERR
Bit 2
T0IF
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TMR2IF TMR1IF 0000 -000 0000 -000
OERR
TRMT
Bit 1
INTF
PIC16F870/871
RX9D
TX9D
Bit 0
R0IF
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
0000 000x
POR, BOR
Value on:
DS30569B-page 77
0000 000u
Value on
RESETS
all other