DSPIC30F3013-30I/SP Microchip Technology, DSPIC30F3013-30I/SP Datasheet - Page 47
DSPIC30F3013-30I/SP
Manufacturer Part Number
DSPIC30F3013-30I/SP
Description
IC DSPIC MCU/DSP 24K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3013-30I/SP
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301330ISP
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F3012-20ISO PDF datasheet #3
- DSPIC30F3012-20ISO PDF datasheet #4
- DSPIC30F3014-30IP PDF datasheet #5
- Current page: 47 of 244
- Download datasheet (7Mb)
4.3
4.3.1
In order to maximize data space, EA calculation and
operand fetch time, the X data space read and write
accesses are partially pipelined. The latter half of the
read phase overlaps the first half of the write phase of
an instruction, as shown in Section 2.
Address register data dependencies, also known as
‘Read After Write’ (RAW) dependencies, may therefore
arise between successive read and write operations
using common registers. They occur across instruction
boundaries and are detected by the hardware.
An example of a RAW dependency is a write operation
(in the current instruction) that modifies W5, followed
by a read operation (in the next instruction) that uses
W5 as a source address pointer. W5 will not be valid for
the read operation until the earlier write completes.
This problem is resolved by stalling the instruction exe-
cution for one instruction cycle, thereby allowing the
write to complete before the next read is started.
TABLE 4-2:
2004 Microchip Technology Inc.
Direct
Direct
Direct
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect with Pre- or
Post-Modification
Indirect with Pre- or
Post-Modification
Indirect with Pre- or
Post-Modification
Addressing Mode
Destination
Using Wn
Instruction Stalls
INTRODUCTION
RAW DEPENDENCY RULES (DETECTION BY HARDWARE)
Direct
Indirect
Indirect with Pre- or
Post-Modification
Direct
Indirect
Indirect
Indirect with Pre- or
Post-Modification
Indirect with Pre- or
Post-Modification
Direct
Indirect
Indirect with Pre- or
Post-Modification
Source Addressing
Mode Using Wn
No Stall ADD.w
No Stall ADD.w
No Stall ADD.w
No Stall ADD.w
No Stall ADD.w
Status
Stall
Stall
Stall
Stall
Stall
Stall
Preliminary
MOV.w
ADD.w
MOV.w
ADD.w
MOV.w
MOV.w
MOV.w
ADD.w
MOV.w
MOV.w
ADD.w
MOV.w
MOV.w
ADD.w
MOV.w
ADD.w
MOV.w
4.3.2
During the instruction pre-decode, the core determines
if any address register dependency is imminent across
an instruction boundary. The stall detection logic com-
pares the W register (if any) used for the destination EA
of the instruction currently being executed, with the W
register to be used by the source EA (if any) of the pre-
fetched instruction. As the W registers are also memory
mapped, the stall detection logic also derives an SFR
address from the W register being used by the destina-
tion EA, and determines whether this address is being
issued during the write phase of the instruction cur-
rently being executed.
When it observes a match between the destination and
source registers, a set of rules are applied to decide
whether or not to stall the instruction by one cycle.
Table 4-2 lists out the various RAW conditions which
cause an instruction execution stall.
[W2++], W3
[W2], W3
W0, W1, [W2] ; W2=0x0004 (mapped W2)
W0, W1, [W2] ; W2=0x0004 (mapped W2)
W0, W1, W2
W2, W3
W0, W1, W2
[W2], W3
W0, W1, W2
[W2++], W3
W0, W1, [W2]
W2, W3
W0, W1, [W2]
[W2], W3
W0, W1, [W2]
[W2++], W3
W0, W1, [W2++]
W2, W3
W0, W1, [W2++]
[W2], W3
W0, W1, [W2++]
[W2++], W3
RAW DEPENDENCY DETECTION
; (i.e., if W2 = addr. of W2)
; (i.e., if W2 = addr. of W2)
(Wn = W2)
Examples
dsPIC30F
DS70082G-page 45
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