PIC16C63A-04I/SP Microchip Technology, PIC16C63A-04I/SP Datasheet - Page 62
![IC MCU OTP 4KX14 PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C63A-04I/SP
Manufacturer Part Number
PIC16C63A-04I/SP
Description
IC MCU OTP 4KX14 PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C63A-04SP.pdf
(184 pages)
2.PIC16C63A-04SP.pdf
(7 pages)
3.PIC16C63A-04SP.pdf
(10 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C63A-04I/SP
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
192Byte
Cpu Speed
4MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVMCPA - KIT DVR BOARD EVAL SYSTEM MXDEV1
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16C63A-04I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16C63A-04SP PDF datasheet
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PIC16C63A/65B/73B/74B
10.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as any situation where a received byte
in SSPBUF is overwritten by the next received byte
before it has been read. An overflow has occurred
when:
FIGURE 10-6:
DS30605C-page 62
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
A7 A6 A5 A4 A3 A2 A1
1
Reception
2
Receiving Address
3
I
4
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
R/W=0
7
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full
4
D3
5
D2
6
a)
b)
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
D1
7
The Buffer Full flag bit, BF(SSPSTAT<0>) was
set, indicating that the byte in SSPBUF was
waiting to be read when another byte was
received. This sets the SSPOV flag.
The overflow flag, SSPOV (SSPCON1<6>) was
set.
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent
D3
2000 Microchip Technology Inc.
5
D2
6
D1
7
D0
8
ACK
9
Bus Master
transfer
terminates
P
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