ATMEGA32A-AU Atmel, ATMEGA32A-AU Datasheet - Page 279

• Manufacturer Part Number: ATMEGA32A-AU
• Description: MCU AVR 32K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 1024 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.14
8155C–AVR–02/11
Parallel Programming Characteristics
Figure 26-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 26-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 26-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
(DATA, XA0/1, BS1, BS2)
XTAL1
PAGEL
XTAL1
DATA
DATA
BS1
XA0
XA1
BS1
XA0
XA1
OE
1. The timing requirements shown in
loading operation.
Data & Contol
Timing Requirements
RDY/BSY
PAGEL
ADDR0 (Low Byte)
LOAD ADDRESS
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
WR
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
(LOW BYTE)
DATA (Low Byte)
READ DATA
Figure 26-7
t
t
t
t
t
XLXH
XLDX
PLBX
XLWL
PLWL
t
BVDV
(that is, t
t
(HIGH BYTE)
BVWL
LOAD DATA
DATA (High Byte)
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
t
DVXH
WL WH
XLPH
WLRL
LOAD DATA
, t
XHXL
t
OHDZ
t
PLXH
, and t
ATmega32A
t
WLBX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
XLDX
(LOW BYTE)
ADDR1 (Low Byte)
ADDR1 (Low Byte)
) also apply to
t
WLRH
(1)
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