DSPIC30F3010-30I/SO Microchip Technology, DSPIC30F3010-30I/SO Datasheet - Page 46
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DSPIC30F3010-30I/SO
Manufacturer Part Number
DSPIC30F3010-30I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3010-30I/SO
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301030ISO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3010-30I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F
4.2.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory. These memory locations are
known as File Registers. Most file register instructions
employ a working register W0, which is denoted as
WREG in these instructions. The destination is typically
either the same file register, or WREG (with the excep-
tion of the MUL instruction), which writes the result to a
register or register pair. The MOV instruction can use a
16-bit address field.
4.2.2
The three-operand MCU instructions are of the form:
where Operand 1 is always a working register (i.e., the
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be W register,
fetched from data memory, or 5-bit literal. In two-
operand instructions, the result location is the same as
that of one of the operands. Certain MCU instructions
are one-operand operations. The following Addressing
modes are supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• 5-bit or 10-bit Literal
4.2.3
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
DS70082G-page 44
Note:
Note:
Operand 3 = Operand 1 <function> Operand 2
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
MOVE AND ACCUMULATOR
INSTRUCTIONS
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared
destination (but typically only used by
one).
between
both
source
and
Preliminary
In summary, the following Addressing modes are
supported by Move and Accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
4.2.4
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The two source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
In summary, the following Addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-modified by 2
• Register Indirect Post-modified by 4
• Register Indirect Post-modified by 6
• Register Indirect with Register Offset (Indexed)
4.2.5
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
Note:
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
MAC INSTRUCTIONS
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
OTHER INSTRUCTIONS
2004 Microchip Technology Inc.