DSPIC33FJ64GP202-I/MM Microchip Technology, DSPIC33FJ64GP202-I/MM Datasheet - Page 60
![IC DSPIC MCU/DSP 64K 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ64GP202-I/MM
Manufacturer Part Number
DSPIC33FJ64GP202-I/MM
Description
IC DSPIC MCU/DSP 64K 28-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 60 of 412
- Download datasheet (6Mb)
TABLE 4-26:
TABLE 4-27:
TABLE 4-28:
TABLE 4-29:
ALRMVAL
ALCFGRPT
RTCVAL
RCFGCAL
PADCFG1
Legend:
CRCCON
CRCXOR
CRCDAT
CRCWDAT
Legend:
CMCON
CVRCON
Legend:
TRISA
PORTA
LATA
ODCA
Legend:
File Name
File Name
File Name
File Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
0630
0632
02C0
02C2
02C4
02C6
Addr
0640
0642
0644
0646
Addr
02FC
0620
0622
0624
0626
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
CRC REGISTER MAP
DUAL COMPARATOR REGISTER MAP
PORTA REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302
CMIDL
ALRMEN
Bit 15
Bit 15
Bit 15
RTCEN
Bit 15
—
—
—
—
—
—
—
Bit 14
Bit 14
Bit 14
CHIME
Bit 14
—
—
—
—
—
—
—
—
—
C2EVT
RTCWREN RTCSYNC HALFSEC
Bit 13
Bit 13
Bit 13
CSIDL
—
Bit 13
—
—
—
—
—
C1EVT
Bit 12
Bit 12
Bit 12
—
—
—
—
—
Bit 12
AMASK<3:0>
—
Bit 11
C2EN
Bit 11
Bit 11
—
—
—
—
—
Bit 11
—
VWORD<4:0>
Bit 10
C1EN
Bit 10
Bit 10
—
—
—
—
—
RTCOE
Bit 10
—
RTCC Value Register Window based on RTCPTR<1:0>
Alarm Value Register Window based on APTR<1:0>
C2OUTEN
Bit 9
Bit 9
—
Bit 9
—
—
—
—
Bit 9
ALRMPTR<1:0>
—
RTCPTR<1:0>
CRC Data Input Register
C1OUTEN
CRC Result Register
Bit 8
Bit 8
Bit 8
—
—
—
—
—
X<15:0>
Bit 8
—
CRCFUL
Bit 7
CVREN
Bit 7
C2OUT
—
—
—
—
Bit 7
Bit 7
—
CRCMPT
Bit 6
CVROE
C1OUT
Bit 6
—
—
—
—
Bit 6
Bit 6
—
Bit 5
Bit 5
C2INV
CVRR
—
—
—
—
Bit 5
—
Bit 5
—
CRCGO
TRISA4
LATA4
CVRSS
Bit 4
C1INV
Bit 4
RA4
Bit 4
—
Bit 4
—
ARPT<7:-0>
CAL<7:0>
C2NEG
TRISA3
LATA3
Bit 3
Bit 3
Bit 3
RA3
—
Bit 3
—
C2POS
TRISA2
LATA2
Bit 2
Bit 2
Bit 2
RA2
Bit 2
—
—
PLEN<3:0>
CVR<3:0>
RTSECSEL PMPTTL
C1NEG
TRISA1
Bit 1
LATA1
Bit 1
Bit 1
Bit 1
RA1
—
C1POS
TRISA0
Bit 0
LATA0
Bit 0
Bit 0
Bit 0
RA0
—
Resets
Resets
Resets
Resets
0000
0000
xxxx
0000
xxxx
0000
0000
0000
0000
0000
0000
001F
xxxx
xxxx
0000
All
All
All
All
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