PIC16F84A-20/SS Microchip Technology, PIC16F84A-20/SS Datasheet - Page 147

IC MCU FLASH 1KX14 EE 20SSOP

PIC16F84A-20/SS

Manufacturer Part Number
PIC16F84A-20/SS
Description
IC MCU FLASH 1KX14 EE 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F84A-20/SS

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
20MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPI3-DB16F84A - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
1997 Microchip Technology Inc.
Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded
from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the
old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed
together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can
clear the interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition, and allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four
pins allow easy interface to a keypad and make it possible for wake-up on key-depression.
The interrupt on change feature is recommended for wake-up on key depression and operations
where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recom-
mended while using the interrupt on change feature.
Figure 9-5: Block Diagram of RB7:RB4 Pins
Any read or write of PORTB. This will end the mismatch condition.
Clear flag bit RBIF.
Note 1: I/O pins have diode protection to V
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
3: In sleep mode the device is in Q1 state.
RB7:RB6 in serial programming mode
Data bus
WR TRIS
WR Port
RBPU
and clear the RBPU bit (OPTION<7>).
Set RBIF
From other
RB7:RB4 pins
(2)
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
CK
CK
Section 9. I/O Ports
Q
Q
DD
Q
Q
Latch
and V
EN
EN
D
D
TTL
Input
Buffer
SS
.
V
P
DD
weak
pull-up
RD Port
Buffer
I/O
pin
Q1
DS31009A-page 9-7
Q3
(1)
ST
9

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