PIC18F2423-I/SP Microchip Technology, PIC18F2423-I/SP Datasheet - Page 26

• Manufacturer Part Number: PIC18F2423-I/SP
• Description: IC PIC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2423-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 12-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2423/2523/4423/4523
TABLE 5-3:
DS39759A-page 26
MCLRE
LPT1OSC
PBADEN
CCP2MX
DEBUG
XINST
LVP
STVREN
CP3
CP2
CP1
CP0
CPD
CPB
WRT3
Bit Name
PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG5H
CONFIG5H
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG5L
CONFIG5L
CONFIG5L
CONFIG5L
CONFIG6L
Words
MCLR Pin Enable bit
1 = MCLR pin enabled, RE3 input pin disabled
0 = RE3 input pin enabled, MCLR pin disabled
Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
PORTB A/D Enable bit
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled
Low-Voltage Programming Enable bit
1 = Low-Voltage Programming enabled, RB5 is the PGM pin
0 = Low-Voltage Programming disabled, RB5 is an I/O pin
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Code Protection bits (Block 3 code memory area)
1 = Block 3 is not code-protected
0 = Block 3 is code-protected
Code Protection bits (Block 2 code memory area)
1 = Block 2 is not code-protected
0 = Block 2 is code-protected
Code Protection bits (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
Code Protection bits (Block 0 code memory area)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
Code Protection bits (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
Code Protection bits (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
Write Protection bits (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-protected
purpose I/O pins
Debug
(Legacy mode)
Description
© 2005 Microchip Technology Inc.