PIC18F2423-I/SP Microchip Technology, PIC18F2423-I/SP Datasheet - Page 381

• Manufacturer Part Number: PIC18F2423-I/SP
• Description: IC PIC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2423-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 12-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DC Characteristics ........................................................... 337
DCFSNZ .......................................................................... 291
DECF ............................................................................... 290
DECFSZ ........................................................................... 291
Development Support ...................................................... 321
Device Differences ........................................................... 373
Device Overview .................................................................. 7
Device Reset Timers .......................................................... 45
Direct Addressing ............................................................... 69
E
Effect on Standard PIC MCU Instructions ........................ 318
Effects of Power-Managed Modes on
Electrical Characteristics .................................................. 325
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Enhanced Universal Synchronous Asynchronous
Equations
Errata ................................................................................... 6
EUSART
© 2007 Microchip Technology Inc.
Power-Down and Supply Current ............................ 328
Supply Voltage ......................................................... 327
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Various Clock Sources ............................................... 31
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Enhanced PWM Mode ............................................. 149
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Special Event Trigger ............................................... 148
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 232
A/D Minimum Charging Time ................................... 232
Asynchronous Mode ................................................ 215
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 209
Associated Registers, Receive ........................ 218
Associated Registers, Transmit ....................... 216
Auto-Wake-up on Sync
Break Character Sequence ............................. 220
Receiver ........................................................... 217
Receiving a Break Character ........................... 220
Setting Up 9-Bit Mode with
Transmitter ....................................................... 215
Operation in Power-Managed Mode ................ 209
Associated Registers ....................................... 210
Auto-Baud Rate Detect .................................... 213
Baud Rate Error, Calculating ........................... 210
Baud Rates, Asynchronous Modes ................. 211
High Baud Rate Select (BRGH Bit) ................. 209
Sampling .......................................................... 209
Break Character ....................................... 218
Address Detect ........................................ 217
PIC18F2423/2523/4423/4523
Preliminary
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 253, 265
Fast Register Stack ........................................................... 56
Flash Program Memory ..................................................... 73
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 292
H
Hardware Multiplier ............................................................ 89
Synchronous Master Mode ...................................... 221
Synchronous Slave Mode ........................................ 224
ADDFSR .................................................................. 314
ADDULNK ............................................................... 314
CALLW .................................................................... 315
Considerations for Use ............................................ 318
MOVSF .................................................................... 315
MOVSS .................................................................... 316
PUSHL ..................................................................... 316
SUBFSR .................................................................. 317
SUBULNK ................................................................ 317
Syntax ...................................................................... 313
Using MPLAB IDE Tools ......................................... 320
Exiting Operation ..................................................... 265
Interrupts in Power-Managed Modes ...................... 266
POR or Wake from Sleep ........................................ 266
WDT During Oscillator Failure ................................. 265
Associated Registers ................................................. 82
Control Registers ....................................................... 74
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing To .................................................................. 79
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89
Associated Registers, Receive ........................ 223
Associated Registers, Transmit ....................... 222
Reception ........................................................ 223
Transmission ................................................... 221
Associated Registers, Receive ........................ 225
Associated Registers, Transmit ....................... 224
Reception ........................................................ 225
Transmission ................................................... 224
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Boundaries Based on Operation ....................... 76
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
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