DSPIC30F3011-20I/PT Microchip Technology, DSPIC30F3011-20I/PT Datasheet
DSPIC30F3011-20I/PT
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DSPIC30F3011-20I/PT Summary of contents
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... Microchip Technology Inc. dsPIC30F3010/3011 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70141E ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Logic • 17-Bit x 17-Bit Single-Cycle Hardware Fractional/ Integer Multiplier • All DSP Instructions Single Cycle • ±16-Bit Single-Cycle Shift © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Peripheral Features: • High-Current Sink/Source I/O Pins: 25 mA/25 mA • Timer module with Programmable Prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F3010 28 24K/8K 1024 dsPIC30F3011 40/44 24K/8K 1024 DS70141E-page 2 CMOS Technology: • Low-Power, High-Speed Flash Technology • Wide Operating Voltage Range (2.5V to 5.5V) • Industrial and Extended Temperature Ranges • Low Power Consumption Output ...
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... PWM3L/RE4 8 33 AN6/OCFA/RB6 PWM3H/RE5 AN7/RB7 AN8/RB8 RF0 RF1 SS 28 OSC1/CLKI 13 U2RX/CN17/RF4 14 27 U2TX/CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 26 PGD/EMUD/U1TX/SDO1/SCL/RF3 16 25 FLTA/INT0/RE8 17 24 SCK1/RF6 18 23 EMUC2/OC1/IC1/INT1/RD0 OC4/RD3 19 22 OC3/RD2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F3011 SS 6 AN8/RB8 AN7/RB7 26 8 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 DS70141E-page 3 ...
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... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 DS70141E-page RF1 5 29 RF0 dsPIC30F3011 OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 © 2008 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 28-Pin SPDIP 28-Pin SOIC EMUD3/AN0/V REF EMUC3/AN1/V REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 4 25 PWM2L/RE2 5 24 PWM2H/RE3 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70141E-page 6 © 2008 Microchip Technology Inc. ...
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... Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for the dsPIC30F3011 and dsPIC30F3010 devices. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The dsPIC30F DS70141E-page 7 ...
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... FIGURE 1-1: dsPIC30F3011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Loop Stack Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... Generation Oscillator Start-up Timer POR/BOR Reset MCLR Watchdog Timer Input 10-Bit ADC Capture Module SPI Timers QEI © 2008 Microchip Technology Inc. dsPIC30F3010/3011 X Data Bus Data Latch Data Latch Y Data X Data RAM RAM 16 (4 Kbytes) (4 Kbytes) Address Address Latch Latch 16 16 ...
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... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F3011 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...
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... TABLE 1-1: dsPIC30F3011 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB8 I/O ST RC13-RC15 I/O ST RD0-RD3 I/O ST RE0-RE5, I/O ST RE8 RF0-RF6 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 I ST ...
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... PWM 3 Low output. PWM 3 High output. Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare outputs 1 and 2. Analog = Analog input Output Power © 2008 Microchip Technology Inc. ...
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... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
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... NOTES: DS70141E-page 14 © 2008 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
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... The upper byte of the SR register contains the DSP adder/subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. © 2008 Microchip Technology Inc. ...
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... Registers AD39 DSP ACCA Accumulators ACCB PC22 TBLPAG Data Table Page Address PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F3010/3011 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 Program Space Visibility Page Address ...
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... Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 Unsigned divide: Wm/Wn → W0; Rem → block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: Instruction CLR ED EDAC MAC MOVSAC MPY MPY.N MSC selection DSP INSTRUCTION SUMMARY Algebraic Operation – – change – – © 2008 Microchip Technology Inc. ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2008 Microchip Technology Inc. dsPIC30F3010/3011 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70141E-page 19 ...
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... OVBTE) in the INTCON1 regis- ter (refer to Section 5.0 “Interrupts”) is set. This allows the user to take immediate action, for example, to correct system gain. © 2008 Microchip Technology Inc. ...
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... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2008 Microchip Technology Inc. ...
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... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, read/write instructions, bit 23 allows access to the Device ID, the User ID and the Configuration bits; otherwise, bit 23 is always clear. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR ...
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... Note: Program Space Visibility cannot be used to access bits<23:16> word in program memory. DS70141E-page 24 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2008 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 A set of table instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address ...
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... Execution prior to exiting the loop due to an Reference interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle space addresses. The © 2008 Microchip Technology Inc. ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Program Space 0x0000 (1) PSVPAG ...
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... Optionally Mapped into Program Memory 0xFFFF DS70141E-page 28 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0xBFE 0x0C00 0x8000 X Data Unimplemented (X) 0xFFFE 3072 Bytes Near Data Space © 2008 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA Using any W © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only ...
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... Fault. FIGURE 3-8: MSB 15 0001 Byte 1 0x0000 Byte 3 0003 0x0000 Byte 5 0005 0x0000 ® DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2008 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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... DS70141E-page 32 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 33 ...
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... NOTES: DS70141E-page 34 © 2008 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F3010/3011 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2008 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F3010/3011 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags, as well register field to specify the W address registers ...
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... W register that has been designated as the Bit-Reversed Pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, should not be enabled © 2008 Microchip Technology Inc. ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Decimal XB<14:0> Bit-Reversed Address Modifier Value Bit-Reversed Address A0 Decimal 0x0100 0x0080 0x0040 ...
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... NOTES: DS70141E-page 40 © 2008 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS Register (SR) in the processor core. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions ...
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... Reserved 37 45 Reserved 38 46 Reserved 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault Reserved 45-53 53-61 Reserved Lowest Natural Order Priority * Available on dsPIC30F3011 only © 2008 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected, which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 5.3 Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1 ...
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... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2008 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 5.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
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... DS70141E-page 46 © 2008 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F3010/3011 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2008 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F3010/3011 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 51 ...
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... NOTES: DS70141E-page 52 © 2008 Microchip Technology Inc. ...
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... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete, but the write time will vary with voltage and temperature. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- ...
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... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2008 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... The NVMADR captures last table access address. ; Select data EEPROM for multi word op ; Operate Key to allow program operation ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle © 2008 Microchip Technology Inc. ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70141E-page 58 © 2008 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR PORT Read LAT Read PORT © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...
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... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISBB NOP BTSS PORTB, #13 I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 61 ...
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... DS70141E-page 62 © 2008 Microchip Technology Inc. ...
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... Bit 6 CNEN1 00C0 CN7IE CN6IE CN5IE CNPU1 00C4 CN7PUE CN6PUE CN5PUE Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Bit 5 Bit 4 Bit 3 Bit 2 CN4IE CN3IE CN2IE CN4PUE CN3PUE CN2PUE CN1PUE ...
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... NOTES: DS70141E-page 64 © 2008 Microchip Technology Inc. ...
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... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal © 2008 Microchip Technology Inc. dsPIC30F3010/3011 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module ...
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... Period register and be reset to 0x0000. When a match between the timer and the Period register occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. TSYNC Sync 1 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2008 Microchip Technology Inc. dsPIC30F3010/3011 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register, and is then reset to ‘0’. ...
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... DS70141E-page 68 © 2008 Microchip Technology Inc. ...
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... Interrupt on a 32-Bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. ...
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... Timer Configuration bit, T32 T2CON(<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70141E-page 70 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... T3IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer3. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 PR2 TMR2 Q D TGATE Q CK ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 73 ...
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... NOTES: DS70141E-page 74 © 2008 Microchip Technology Inc. ...
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... The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are as follows: • ...
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... The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) DS70141E-page 76 PR4 TMR4 Q D TGATE CK Q TON 1 x Gate Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 PR5 Comparator x 16 TMR5 Q D TGATE ...
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... DS70141E-page 78 © 2008 Microchip Technology Inc. ...
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... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels, 1 through N. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the input capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...
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... The capture module must be configured for interrupt only on the rising edge (ICM<2:0> = 111) in order for the input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2008 Microchip Technology Inc. ...
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... ICSIDL bit must be asserted to a logic ‘0’. If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt based upon the selected number of capture events ...
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... DS70141E-page 82 © 2008 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through N. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2008 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • ...
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... DS70141E-page 86 © 2008 Microchip Technology Inc. ...
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... INDX Digital Filter 3 Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
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... UPDN signal is supplied to a SFR bit, UPDN (QEICON<11>), as a read-only bit. Note: QEI pins are multiplexed with analog inputs. The user must insure that all QEI associ- ated pins are set as digital inputs in the ADPCFG register. © 2008 Microchip Technology Inc. ...
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... CY To enable the filter output for channels, QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 14.5 Alternate 16-Bit Timer/Counter When the QEI module is not configured for the QEI mode, QEIM< ...
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... The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 register. Enabling an interrupt is accomplished via the respec- tive enable bit, QEIIE. The QEIIE bit is located in the IEC2 register. © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 91 ...
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... NOTES: DS70141E-page 92 © 2008 Microchip Technology Inc. ...
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... Uninterruptible Power Supply (UPS) The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution © 2008 Microchip Technology Inc. dsPIC30F3010/3011 • ‘On-the-Fly’ PWM frequency changes • Edge and Center-Aligned Output modes • ...
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... Generator and Override Logic PWM Generator Channel 2 Dead-Time #2 Generator and Override Logic PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler PTDIR PWM3H PWM3L PWM2H Output PWM2L Driver Block PWM1H PWM1L FLTA Special Event Trigger © 2008 Microchip Technology Inc. ...
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... Motors (ECMs). The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
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... COUNTING MODE) • • (PTPER + 0.75 PWM (PTMR Prescale Value) The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-3: EQUATION 15-3: PWM RESOLUTION • log ( PWM Resolution = log (2) © 2008 Microchip Technology Inc. using ) CY ...
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... PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to the value held in the PTPER register. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 15-3: CENTER-ALIGNED PWM ...
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... On a load of the down timer due to a duty cycle comparison edge event. • write to the DTCON1 register. • On any device Reset. Note: The user should not modify the DTCON1 value while the PWM module is operating (PTEN = 1). Unexpected results may occur. © 2008 Microchip Technology Inc. ) may be CY ...
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... FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Dead Time © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Dead Time DS70141E-page 99 ...
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... OVDCON register are synchronized to the PWM time base. Synchronous output overrides occur at the following times: • Edge-Aligned mode, when PTMR is zero. • Center-Aligned modes, when PTMR is zero and when the value of PTMR matches PTPER. © 2008 Microchip Technology Inc. six bits, ...
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... Fault pin could be used as a general purpose interrupt pin. The Fault pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 15.12.2 FAULT STATES The FLTACON Special Function Register has 6 bits that determine the state of each PWM I/O pin when it is overridden by a Fault input ...
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... The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode. If PTSIDL = 0, the module will continue to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in Idle mode. © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 103 ...
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... NOTES: DS70141E-page 104 © 2008 Microchip Technology Inc. ...
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... If any trans- mit data has been written to the buffer register, the © 2008 Microchip Technology Inc. dsPIC30F3010/3011 contents of the transmit buffer are moved to SPI1SR. The received data is thus placed in SPI1BUF and the transmit data in SPI1SR is ready for the next transfer ...
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... Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler Prescaler CY 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2008 Microchip Technology Inc. ...
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... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 has been deasserted in the middle of a transmit/receive. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down ...
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... DS70141E-page 108 © 2008 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 17.1.1 VARIOUS I The following types • Slave operation with 7-bit addressing 2 • Slave operation with 10-bit addressing 2 • ...
Page 112
... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2008 Microchip Technology Inc. ...
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... SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 114
... C bus have deasserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2008 Microchip Technology Inc. ...
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... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific general call address. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2 17. Master Support As a master device, six operations are supported: ...
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... C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle master event Interrupt Service 2 C bus is free (i.e., the P bit is set), the 2 C bus © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 115 ...
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... NOTES: DS70141E-page 116 © 2008 Microchip Technology Inc. ...
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... UTXBRK Data UxTX Parity Note dsPIC30F3010 only has UART1. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
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... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2008 Microchip Technology Inc. ...
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... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18.3 Transmitting Data 18.3.1 ...
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... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2008 Microchip Technology Inc. RXB) ...
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... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
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... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 123 ...
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... NOTES: DS70141E-page 124 © 2008 Microchip Technology Inc. ...
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... The ADC has a unique feature of REF REF being able to operate while the device is in Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • ...
Page 128
... AN1 Note 1: Not available on dsPIC30F3010 devices. DS70141E-page 126 + CH1 ADC S/H - 10-Bit Result + CH2 S/H - 16-word, 10-bit Dual Port + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence Sample Input Switches + CH0 S/H - © 2008 Microchip Technology Inc. Conversion Logic Buffer Control Input Mux Control ...
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... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The CHPS bits select how many channels are sam- pled. This can vary from channels. If the CHPS bits select 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
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... AD . The source of the A/D CONVERSION CLOCK • (0.5 • (ADCS<5:0> – time AD = 5V). Refer to Section 23.0 DD under AD A/D CONVERSION CLOCK CALCULATION T = 154 nsec nsec (30 MIPS – 154 nsec = 2 • – nsec = 8. (ADCS<5:0> nsec = ( 165 nsec © 2008 Microchip Technology Inc. ...
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... Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 19-2 for recommended REF REF circuit. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Table 19-1 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 500Ω ...
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... The ADC converts the value held on one S/H channel, while the second S/H channel acquires a new input sample. DS70141E-page 130 Figure 19-2 depicts the recommended circuit for the conversion rates above 500 ksps dsPIC30F3011 ...
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... ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 19.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled ...
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... Refer to the Section 23.0 "Electrical Characteristics" for T sample time requirements source V DD ≤ 250Ω Sampling Switch LEAKAGE V = 0.6V T ± 500 nA negligible if Rs ≤ 5 kΩ. PIN period of sampling AD and AD ≤ 3 kΩ HOLD = DAC capacitance = 4 © 2008 Microchip Technology Inc. ...
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... Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
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... Any external components connected (via high-impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. and V as ESD the input voltage exceeds this SS © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 135 ...
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... NOTES: DS70141E-page 136 © 2008 Microchip Technology Inc. ...
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... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
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... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70141E-page 138 Description (1) . (2) . (1) . (1) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2008 Microchip Technology Inc. ...
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... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F3010/3011 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer ...
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... OSC2 Function I/O I OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 I/O OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2008 Microchip Technology Inc. ...
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... Table 20-4). If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier (respectively) is applied © 2008 Microchip Technology Inc. dsPIC30F3010/3011 . Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
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... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: : Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2008 Microchip Technology Inc. ...
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... POR timer and place the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Different registers are affected in different ways by various Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70141E-page 144 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2008 Microchip Technology Inc. ...
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... Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
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... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70141E-page 146 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2008 Microchip Technology Inc. ...
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... PWRSAV. These are: Sleep and Idle. The format of the PWRSAV instruction is as follows: PWRSAV <parameter>, where ‘parameter’ defines Idle or Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 20.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shut down ...
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... For additional information, please refer to the programming specifications of the device. Note: If the code protection Configuration bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V DD the Configuration bits is ≥ 4.5V. © 2008 Microchip Technology Inc. ...
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... MPLAB IDE. These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line ...
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... DS70141E-page 150 © 2008 Microchip Technology Inc. ...
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... The File register specified by the value ‘f’ • The destination, which could either be the File register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
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... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). Description © 2008 Microchip Technology Inc. ...
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... Y data space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Description DS70141E-page 153 ...
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... Branch if Accumulator B Overflow Branch if Overflow Branch if Accumulator A Saturated Branch if Accumulator B Saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws © 2008 Microchip Technology Inc Status Flags cycle Affected OA,OB,SA, C,DC,N,OV,Z 1 ...
Page 157
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
Page 158
... Move 8-bit Literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and Store Accumulator Multiply Accumulator Square Wm to Accumulator Multiply and Subtract from Accumulator © 2008 Microchip Technology Inc Status Flags cycle Affected N,Z, ...
Page 159
... SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 160
... Wn = Nibble Swap Byte Swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws © 2008 Microchip Technology Inc Status Flags cycle Affected C,N,OV C,N,OV,Z 1 ...
Page 161
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F3010/3011 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2008 Microchip Technology Inc. ...
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... REAL ICE offers significant advantages over competi- tive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 164
... K L security ICs, CAN ® IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2008 Microchip Technology Inc. ® ...
Page 165
... Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2008 Microchip Technology Inc. dsPIC30F3010/3011 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 166
... T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2008 Microchip Technology Inc. ...
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... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory DD are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 168
... MIPS LPRC (512 kHz) 1.8 MIPS FRC (7.37MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS © 2008 Microchip Technology Inc. ...
Page 169
... These parameters are characterized but not tested in manufacturing. 3: These values represent the difference between the base power-down current and the power-down current with the specified peripheral enabled during Sleep. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 170
... Units Conditions SMbus disabled DD V SMbus enabled SMbus disabled V SMbus enabled μ 5V PIN SS μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD μA ≤ V ≤ XT PIN DD and LP Oscillator mode © 2008 Microchip Technology Inc. ...
Page 171
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) Reset (due to BOR) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 172
... Industrial A ≤ +125°C for Extended A Conditions -40°C ≤ T ≤ +85°C A Using EECON to read/write V = Minimum operating MIN voltage are violated Row Erase -40°C ≤ T ≤ +85° Minimum operating MIN voltage are violated Row Erase Bulk Erase © 2008 Microchip Technology Inc. ...
Page 173
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Pin FIGURE 23-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Operating voltage V ...
Page 174
... MHz XTL MHz XT MHz XT with 4x PLL MHz XT with 8x PLL MHz XT with 16x PLL MHz HS kHz LP MHz FRC internal kHz LPRC internal — See parameter OS10 for F value OSC ns See Table 23- See parameter DO31 ns See parameter DO32 ). CY © 2008 Microchip Technology Inc. ...
Page 175
... Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ T ...
Page 176
... CY * PLLx)/4 since there are 4 Q clocks per instruction cycle. OSC (3) (3) MIPS MIPS w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — © 2008 Microchip Technology Inc. ...
Page 177
... Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 23-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F3010/3011 -40°C ≤ -40°C ≤ Min Typ Max Units (1) -40°C ≤ T — ...
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... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1,2,3) (4) Min Typ Max — — — — — — CY Units Conditions OSC © 2008 Microchip Technology Inc. ...
Page 179
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 23-1 and Table 23-10 for BOR. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SY10 SY13 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 180
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> status bit © 2008 Microchip Technology Inc. ...
Page 181
... SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 182
... T — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2008 Microchip Technology Inc. ...
Page 183
... Period TQ20 T Delay from External TQCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 TQ11 TQ10 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 184
... Industrial ≤ +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See parameter DO32 ns See parameter DO31 © 2008 Microchip Technology Inc. ...
Page 185
... T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max Units — ...
Page 186
... T Operating temperature -40°C ≤ T (1) Min Typ Max Units — — — ns — — — ns — — — — ns ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions See parameter DO32 See parameter DO31 © 2008 Microchip Technology Inc. ...
Page 187
... Note 1: These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” in the”dsPIC30F Family Reference Manual” (DS70046). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 TQ36 TQ30 TQ31 TQ35 ...
Page 188
... T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1) Min Max Units — — — CY Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) ns © 2008 Microchip Technology Inc. ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SP10 SP21 SP20 SP20 ...
Page 190
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns — ns © 2008 Microchip Technology Inc. ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SP70 SP72 SP73 SP72 ...
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... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb In SP41 SP40 Note: Refer to Figure 23-2 for load conditions. DS70141E-page 190 SP70 SP73 SP72 SP35 SP73 SP72 SP52 BIT14 - - - - - -1 LSb BIT14 - - - -1 LSb In SP52 SP51 © 2008 Microchip Technology Inc. ...
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... The minimum clock period for SCx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
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... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-2 for load conditions. DS70141E-page 192 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 © 2008 Microchip Technology Inc. ...
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... BRG is the value of the I C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit (I in the”dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
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... MHz μs Device must operate at a minimum of 10 MHz. μs μs Device must operate at a minimum of 1.5 MHz μs Device must operate at a minimum of 10 MHz μ specified to be from 400 specified to be from 400 © 2008 Microchip Technology Inc. ...
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... BF SDA IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
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... Source Impedance = 5 kΩ μ 0V, INL SS REFL REFH Source Impedance = 5 kΩ Ω bits LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH © 2008 Microchip Technology Inc. ...
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... These parameters are characterized but not tested in manufacturing. 2: Measurements taken with external V 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... Section 17, “10-Bit A/D Converter” of the “dsPIC30F Family Reference Manual”, (DS70046). SAMP 3 — Software clears ADCON. SAMP to start conversion. 4 — Sampling ends, conversion sequence starts. 5 — Convert bit 9. 6 — Convert bit 8. 8 — Convert bit 0. 9 — One T for end of conversion. AD DS70141E-page 198 AD55 AD55 © 2008 Microchip Technology Inc. ...