DSPIC30F3011-20I/PT Microchip Technology, DSPIC30F3011-20I/PT Datasheet - Page 145

• Manufacturer Part Number: DSPIC30F3011-20I/PT
• Description: IC DSPIC MCU/DSP 24K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301120IPT

20.3
The dsPIC30F3010/3011 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 20-2:
20.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
© 2008 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset cause by trap lockup (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
MCLR
V
Illegal Opcode/
Uninitialized W Register
DD
Reset
DD
Instruction
RESET
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
1.85V.
TRAP Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
The
RESET SYSTEM BLOCK DIAGRAM
Rise
device
BOREN
Glitch Filter
Digital
POR
supply
POR
), which is
BOR
voltage
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 20-5. These bits
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 20-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up T
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock, and the PC will
jump to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
dsPIC30F3010/3011
S
R
PWRT
) is applied. The T
Q
POR
DS70141E-page 143
+ T
SYSRST
POR
PWRT
, which is
. When
PWRT