PIC18F4423-I/P Microchip Technology, PIC18F4423-I/P Datasheet - Page 305
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4423-I/P
Manufacturer Part Number
PIC18F4423-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18F4423-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4423-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4423-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4423-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2423-ISP PDF datasheet #2
- PIC18F2423-ISP PDF datasheet #3
- PIC18F2423-ISP PDF datasheet #4
- PIC18F2523-ISO PDF datasheet #5
- Current page: 305 of 392
- Download datasheet (7Mb)
RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
After Instruction:
operation
Decode
PC = TOS
Q1
No
operation
operation
Return from Subroutine
RETURN {s}
s ∈ [0,1]
(TOS) → PC
if s = 1
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
1
2
RETURN
0000
Q2
No
No
0000
operation
Process
Data
Q3
No
0001
from stack
operation
POP PC
PIC18F2423/2523/4423/4523
Q4
No
001s
Preliminary
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
C, N, Z
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
1
1
Rotate Left f through Carry
RLCF
RLCF
Read
0011
Q2
1110 0110
0
1110 0110
1100 1100
1
C
f {,d {,a}}
01da
Process
REG, 0, 0
Data
Q3
DS39755B-page 303
register f
ffff
destination
Write to
Q4
ffff
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