PIC18F8410-I/PT Microchip Technology, PIC18F8410-I/PT Datasheet
PIC18F8410-I/PT
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PIC18F8410-I/PT Summary of contents
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... Refer to Section 6.0 “AC/DC Characteristics • PIC18F8393 Program/Verify Test Mode” for additional hardware • PIC18F8493 parameters. 2.2 Pin Diagrams The pin diagrams for the PIC18F8410/8490/8493 family are shown in Figure 2-1 through Figure 2-4. can be applies to During Programming Pin Type ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 2-1: PIC18F6X10 FAMILY PIN DIAGRAM RE1/WR 1 RE0/RD 2 RG0/CCP3 3 RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3 6 RG5/MCLR RG4 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT Note 1: RE7 is the alternate pin for CCP2 multiplexing. DS39624C-page PIC18F6X10 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 2-2: PIC18F8X10 FAMILY PIN DIAGRAM RH2/A18 1 RH3/A19 2 RE1/AD9/WR 3 RE0/AD8/RD 4 RG0/CCP3 5 RG1/TX2/CK2 6 RG2/RX2/DT2 7 RG3 8 RG5/MCLR RG4 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 Note 1: RE7 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc PIC18F8X10 ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 2-3: PIC18F6X90/6X93 FAMILY PIN DIAGRAM LCDBIAS2 1 LCDBIAS1 2 RG0/SEG30 3 RG1/TX2/CK2/SEG29 4 RG2/RX2/DT2/SEG28 5 RG3/SEG27 6 RG5/MCLR RG4/SEG26 RF7/SS/SEG25 11 RF6/AN11/SEG24 12 RF5/AN10/CV /SEG23 REF 13 RF4/AN9/SEG22 14 RF3/AN8/SEG21 15 RF2/AN7/C1OUT/SEG20 16 Note 1: RE7 is the alternate pin for CCP2 multiplexing. DS39624C-page PIC18F6X90 PIC18F6X93 RB0/INT0 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9 46 RB3/INT3/SEG10 45 RB4/KBI0/SEG11 44 RB5/KBI1 ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 2-4: PIC18F8X90/8X93 FAMILY PIN DIAGRAM 80 79 RH2/SEG45 1 RH3/SEG44 2 LCDBIAS2 3 LCDBIAS1 4 RG0/SEG30 5 RG1/TX2/CK2/SEG29 6 RG2/RX2/DT2/SEG28 7 RG3/SEG27 8 RG5/MCLR RG4/SEG26 RF7/SS/SEG25 13 RF6/AN11/SEG24 14 RF5/AN10/CV /SEG23 REF 15 RF4/AN9/SEG22 16 RF3/AN8/SEG21 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: RE7 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc. ...
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... PIC18F8410/8490/8493 FAMILY 2.3 Memory Map The code memory space extends from 000000h to 001FFFh (8 Kbytes single PIC18FX310/X390/X393 devices and from 000000h to 003FFFh (16 Kbytes single PIC18FX410/X490/X493 devices. TABLE 2-2 IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) PIC18F6310 PIC18F8310 PIC18F6390 000000h-001FFFh (8K) PIC18F6393 PIC18F8390 ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 2-5: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX310/X390/X393 DEVICES 000000h Block 0 001FFFh Unimplemented Read as ‘0’ 200000h 200007h 300000h 30000Dh 3FFFFEh 3FFFFFh Note: Sizes of memory areas are not to scale. © 2007 Microchip Technology Inc. Code Memory ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 2-6: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX410/X490/X493 DEVICES 000000h Block 0 003FFFh Unimplemented Read as ‘0’ 200000h 200007h 300000h 30000Dh 3FFFFEh 3FFFFFh Note: Sizes of memory areas are not to scale. DS39624C-page 8 Code Memory User ID Space Configuration Bits Space ...
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... PIC18F8410/8490/8493 FAMILY 2.4 High-Level Overview of the Programming Process Figure 2-8 shows the high-level overview of the programming process. The device is first checked to see blank not, a Chip Erase is performed. Next, the code memory and ID locations are programmed. These memories are then verified to ensure that programming was successful errors ...
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... PIC18F8410/8490/8493 FAMILY 2.6 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC and are Least Significant bit (LSb) first ...
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... Checking” a device merely means to verify that all bytes read as FFh, except the configuration bits. Unused (reserved) configuration bits will read as ‘0’. Refer to Table 5-3 for blank configuration except data for the various PIC18F8410/8490/8493 family devices. locations and determined that the device is not blank, then the ...
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... PIC18F8410/8490/8493 FAMILY 3.2 High-Voltage ICSP Chip Erase Erasing code is accomplished by writing an “erase option” to address 3C0004h. Code memory is erased by erasing the entire device in one action. “Chip Erase” operations will also clear any code-protect settings. Chip Erase is detailed in Table 3-1. TABLE 3-1 ...
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... PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. The code sequence PIC18F8410/8490/8493 family device is shown in Table 3-3. The flowchart shown in Figure 3-6 depicts the logic necessary PIC18F8410/8490/8493 family device. The timing diagram that details the “Start Programming” command and parameter P10, is shown in Figure 3-7 ...
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... PIC18F8410/8490/8493 FAMILY TABLE 3-3 WRITE CODE MEMORY CODE SEQUENCE 4-Bit Data Payload Command Step 1: Direct access to code memory and enable writes. 0000 9C A6 0000 84 A6 Step 2: Load write buffer. 0000 0E <Addr[21:16]> 0000 6E F8 0000 0E <Addr[15:8]> 0000 6E F7 0000 0E <Addr[7:0]> 0000 6E F6 1101 < ...
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... PIC18F8410/8490/8493 FAMILY FIGURE 3-7: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command 3.4 ID Location Programming The ID locations are programmed much like the code memory. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally, even after code protection. ...
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... PIC18F8410/8490/8493 FAMILY 3.5 Boot Block Programming The PIC18F8410/8490/8493 family devices do not have any Boot Block segment. PIC18F8310/8410 devices are Microprocessor with Boot Block mode, the locations from 0000h to 07FFh will be internal memory. This memory region is programmed in exactly the same manner as the code memory (see Section 3.3 “Code Memory Programming” ...
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... PIC18F8410/8490/8493 FAMILY 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations and Configuration Bits Code memory is accessed one byte at a time via the 4-bit command, ‘1001’ (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) is serially output on PGD ...
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... PIC18F8410/8490/8493 FAMILY 4.2 Verify Code Memory and ID Locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 4.1 “ ...
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... ID space, the ID data will execute as a NOP. 5.2 Device ID Word The device ID word for the PIC18F8410/8490/8493 family is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read-protected ...
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... DEVID2 DEV10 DEV9 Legend unknown unchanged unimplemented value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F8410/8490/8493 family devices; maintain the default unprogrammed value. 2: DEVIDx registers are read-only and cannot be programmed by the user. DS39624C-page 20 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... BOREN1:BOREN0 CONFIG2L BORV1:BORV0 CONFIG2L WDTEN CONFIG2H Note 1: Unimplemented in PIC18F8410/8490/8493 family devices; maintain the default unprogrammed value. © 2007 Microchip Technology Inc. Description Oscillator Selection bits 1111 = External RC oscillator w/ OSC2 configured as ‘divide by 4 clock output’ 1110 = External RC oscillator w/ OSC2 configured as ‘divide by 4 clock output’ ...
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... CCP2MX CONFIG3H LPT1OSC CONFIG3H MCLRE CONFIG3H STVREN CONFIG4L XINST CONFIG4L Note 1: Unimplemented in PIC18F8410/8490/8493 family devices; maintain the default unprogrammed value. DS39624C-page 22 Description Watchdog Timer Postscaler Select bits 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 ...
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... DEV10:DEV3 DEVID2 DEV2:DEV0 DEVID1 REV4:REV0 DEVID1 Note 1: Unimplemented in PIC18F8410/8490/8493 family devices; maintain the default unprogrammed value. © 2007 Microchip Technology Inc. Description Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger enabled Code Protection bit (code memory area 0000h-3FFFh for PIC18FX410/X490/X493 devices and 0000h-1FFFh for ...
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... PIC18F8410/8490/8493 FAMILY 5.3 Embedding Configuration Word Information in the Hex File To allow portability of code, a PIC18F8410/8490/8493 family device programmer is required to read the Configuration Word locations from the Hex file. If Configuration Word information is not present in the Hex file, then a simple warning message should be issued. Similarly, while saving a Hex file, all Configuration Word information must be included ...
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... PIC18F8410/8490/8493 FAMILY 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25°C is recommended Param Symbol Characteristic No. D110 V High-Voltage Programming Voltage on IHH MCLR/V PP D111 V Supply Voltage During Programming DD D112 I Programming Current on MCLR/V PP D113 I Supply Current During Programming ...
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... PIC18F8410/8490/8493 FAMILY NOTES: DS39624C-page 26 © 2007 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...